summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
diff options
context:
space:
mode:
authorTom Rini <trini@ti.com>2014-02-26 16:49:58 -0500
committerTom Rini <trini@ti.com>2014-02-26 16:49:58 -0500
commiteeb72e67619b98d2502fe634a3a5d9953de92ad0 (patch)
treeedea4b04062ec956158c163b13c9a31fcfdccde8 /arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
parent715b56fe2b47e073e6f2425e0cedba0e92a4014d (diff)
parent1551df35f296f0a8df32f4f2054254f46e8be252 (diff)
downloadu-boot-imx-eeb72e67619b98d2502fe634a3a5d9953de92ad0.zip
u-boot-imx-eeb72e67619b98d2502fe634a3a5d9953de92ad0.tar.gz
u-boot-imx-eeb72e67619b98d2502fe634a3a5d9953de92ad0.tar.bz2
Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts: arch/arm/cpu/armv7/config.mk board/ti/am43xx/mux.c include/configs/am43xx_evm.h Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/at91/lowlevel_init.S')
-rw-r--r--arch/arm/cpu/arm926ejs/at91/lowlevel_init.S14
1 files changed, 1 insertions, 13 deletions
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
index e83968f..a9ec81a 100644
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
@@ -26,27 +26,18 @@
#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
#endif
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
.globl lowlevel_init
.type lowlevel_init,function
lowlevel_init:
- mov r5, pc /* r5 = POS1 + 4 current */
POS1:
+ adr r5, POS1 /* r5 = POS1 run time */
ldr r0, =POS1 /* r0 = POS1 compile */
- ldr r2, _TEXT_BASE
- sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
- sub r5, r5, #4 /* r1 = text base - current */
/* memory control configuration 1 */
ldr r0, =SMRDATA
ldr r2, =SMRDATA1
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
0:
@@ -149,9 +140,6 @@ PLL_setup_end:
ldr r0, =SMRDATA1
ldr r2, =SMRDATA2
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
2: