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authorYe Li <ye.li@nxp.com>2016-03-09 16:13:48 +0800
committerStefano Babic <sbabic@denx.de>2016-03-25 13:55:54 +0100
commitb777789ebd193587a8e4700dce656523df821370 (patch)
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parent312a6c016a2d81aa3fbc605f5c0c315b6a4e3464 (diff)
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imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
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