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| author | Alexey Brodkin <abrodkin@synopsys.com> | 2015-02-03 13:58:13 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2015-02-09 16:41:20 +0300 |
| commit | 205e7a7b77726abeff57576e2ecf2c6d4dc07ccf (patch) | |
| tree | 5f3bae0b6a43d741cb1aabf10f541b6ec38b921e /arch/arc/include/asm | |
| parent | 5ff40f3d4226d45c78f3bb9db276f6685b24a89a (diff) | |
| download | u-boot-imx-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.zip u-boot-imx-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.tar.gz u-boot-imx-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.tar.bz2 | |
arc: select cache settings via menuconfig
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.
It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 368d1f0..2725961 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -9,15 +9,12 @@ #include <config.h> -/* - * The current upper bound for ARC L1 data cache line sizes is 128 bytes. - * We use that value for aligning DMA buffers unless the board config has - * specified an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#ifdef CONFIG_ARC_CACHE_LINE_SHIFT +#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT) +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #else -#define ARCH_DMA_MINALIGN 128 +/* Satisfy users of ARCH_DMA_MINALIGN */ +#define ARCH_DMA_MINALIGN 128 #endif #if defined(CONFIG_ARC_MMU_V2) |