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authorPriyanka Jain <Priyanka.Jain@freescale.com>2013-04-04 09:31:54 +0530
committerAndy Fleming <afleming@freescale.com>2013-06-20 16:09:08 -0500
commit765b0bdb899d614d0455f19548901b79f2baa66c (patch)
tree7508adf27d2e7f7ae32c925ba555f33528a1b1e8 /README
parent087cf44fcd237d965ecccd6cf9e52de8d3c51a2e (diff)
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board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'README')
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diff --git a/README b/README
index c3d6ca5..2dd0bc0 100644
--- a/README
+++ b/README
@@ -422,6 +422,13 @@ The following options need to be configured:
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
+ CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+ This value denotes start offset of M2 memory
+ which is directly connected to the DSP core.
+
+ CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+ This value denotes start offset of DSP CCSR space.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN