From 765b0bdb899d614d0455f19548901b79f2baa66c Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 4 Apr 2013 09:31:54 +0530 Subject: board/bsc9131rdb: Add DSP side tlb and laws BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming --- README | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'README') diff --git a/README b/README index c3d6ca5..2dd0bc0 100644 --- a/README +++ b/README @@ -422,6 +422,13 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. + CONFIG_SYS_FSL_DSP_M2_RAM_ADDR + This value denotes start offset of M2 memory + which is directly connected to the DSP core. + + CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT + This value denotes start offset of DSP CCSR space. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN -- cgit v1.1