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| author | York Sun <yorksun@freescale.com> | 2014-02-10 13:59:44 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 11:06:13 -0500 |
| commit | 6b1e1254f326940e5b65c7029f71b964bdf28fd4 (patch) | |
| tree | a8e596b2d01fe4a952e253b9b42972b040a4a165 /README | |
| parent | 6b9e309a8a7f0f33252288f0ed8794a83a488301 (diff) | |
| download | u-boot-imx-6b1e1254f326940e5b65c7029f71b964bdf28fd4.zip u-boot-imx-6b1e1254f326940e5b65c7029f71b964bdf28fd4.tar.gz u-boot-imx-6b1e1254f326940e5b65c7029f71b964bdf28fd4.tar.bz2 | |
driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -497,6 +497,11 @@ The following options need to be configured: same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. + CONFIG_SYS_FSL_DDR_INTLV_256B + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape + SoCs with ARM core. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO |