From 6b1e1254f326940e5b65c7029f71b964bdf28fd4 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 13:59:44 -0800 Subject: driver/ddr: Add 256 byte interleaving support Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun --- README | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README') diff --git a/README b/README index 355e898..f51f17e 100644 --- a/README +++ b/README @@ -497,6 +497,11 @@ The following options need to be configured: same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. + CONFIG_SYS_FSL_DDR_INTLV_256B + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape + SoCs with ARM core. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO -- cgit v1.1