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authorPeng Fan <Peng.Fan@freescale.com>2015-06-25 10:32:26 +0800
committerStefano Babic <sbabic@denx.de>2015-07-26 12:17:20 +0200
commit4683b220655937e8f3c360f4aa25274abed76e0d (patch)
treec13be006ab09dfa367994091437576482b112725 /Licenses
parent42acd1874f3db6c34264870047500435ca01fcda (diff)
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mmc:fsl_esdhc invalidate dcache before read
DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
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