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authorpoonam aggrwal <poonam.aggrwal@freescale.com>2014-05-31 00:08:18 +0530
committerYork Sun <yorksun@freescale.com>2014-06-05 13:45:07 -0700
commitfa6e742825f1e1e00ac69c6829e75f14a1a51e9f (patch)
tree578990ad428e836f2e54431c60400b882414221e
parentb6808cd82d616bec2c357fb1b95116efe5b6f98c (diff)
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powerpc/B4420: Fixed incomplete handling for 0x9d serdes2
Crossbars and IDT were not getting configured for Serdes2 protocol 0x9d for B4420. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r--board/freescale/b4860qds/b4860qds.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index b2d5378..9d6b9a7 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -488,6 +488,9 @@ int configure_vsc3316_3308(void)
}
switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
case 0x9E:
case 0x9A:
case 0x98:
@@ -852,6 +855,9 @@ int config_serdes2_refclks(void)
* For this SerDes2's Refclk1 need to be set to 100MHz
*/
switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
case 0x9E:
case 0x9A:
case 0xb2: