davinci: split out some dm644x-specific bits from psc

Split out DaVinci DM6446-specific bits from more generic bits:

 - Add a CONFIG_SOC_DM644X.  All current boards use DM6446 chips;
   DM6443 and DM6441 chips differ in available peripherals.

 - Move most DM644X-specific bits from psc.c to a new dm644x.c file,
   which is conditionally built.  It provides device-specific setup.

Plus minor coding style and comment updates with respect to the PSC.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

7 files changed, 127 insertions, 75 deletions

diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index e09874b..6052e02 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).a
 
 COBJS-y				+= timer.o psc.o
+COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= ether.o lxt972.o dp83848.o
 
 SOBJS	= reset.o
diff --git a/cpu/arm926ejs/davinci/dm644x.c b/cpu/arm926ejs/davinci/dm644x.c
new file mode 100644
index 0000000..df382bd
--- /dev/null
+++ b/cpu/arm926ejs/davinci/dm644x.c
@@ -0,0 +1,94 @@
+/*
+ * SoC-specific code for tms320dm644x chips
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+#define PINMUX0_EMACEN (1 << 31)
+#define PINMUX0_AECS5  (1 << 11)
+#define PINMUX0_AECS4  (1 << 10)
+
+#define PINMUX1_I2C    (1 <<  7)
+#define PINMUX1_UART1  (1 <<  1)
+#define PINMUX1_UART0  (1 <<  0)
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= PINMUX1_UART0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable EMAC. */
+	REG(PINMUX0) |= PINMUX0_EMACEN;
+}
+#endif
+
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= PINMUX1_I2C;
+}
+
+void davinci_errata_workarounds(void)
+{
+	/*
+	 * Workaround for TMS320DM6446 errata 1.3.22:
+	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
+	 *   Revision(s) Affected: 1.3 and earlier
+	 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/*
+	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
+	 * as suggested in TMS320DM6446 errata 2.1.2:
+	 *
+	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
+	 * low priority modules can occupy the bus and prevent high priority
+	 * modules like the VPSS from getting the required DDR2 throughput.
+	 * A hex value of 0x20 should provide a good ARM (cache enabled)
+	 * performance and still allow good utilization by the VPSS or other
+	 * modules.
+	 */
+	REG(VBPR) = 0x20;
+}
diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c
index 28e2a4b..5bb972f 100644
--- a/cpu/arm926ejs/davinci/psc.c
+++ b/cpu/arm926ejs/davinci/psc.c
@@ -26,22 +26,22 @@
 #include <common.h>
 #include <asm/arch/hardware.h>
 
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5  (1 << 11)
-#define PINMUX0_AECS4  (1 << 10)
-
-#define PINMUX1_I2C    (1 <<  7)
-#define PINMUX1_UART1  (1 <<  1)
-#define PINMUX1_UART0  (1 <<  0)
-
 /*
- * The DM6446 includes two separate power domains: "Always On" and "DSP". The
- * "Always On" power domain is always on when the chip is on. The "Always On"
- * domain is powered by the VDD pins of the DM6446. The majority of the
- * DM6446's modules lie within the "Always On" power domain. A separate
- * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain
- * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of
- * the DM6446.
+ * The PSC manages three inputs to a "module" which may be a peripheral or
+ * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
+ * its power domain.  For our purposes, we only care whether clock and power
+ * are active, and the module is out of reset.
+ *
+ * DaVinci chips may include two separate power domains: "Always On" and "DSP".
+ * Chips without a DSP generally have only one domain.
+ *
+ * The "Always On" power domain is always on when the chip is on, and is
+ * powered by the VDD pins (on DM644X). The majority of DaVinci modules
+ * lie within the "Always On" power domain.
+ *
+ * A separate domain called the "DSP" domain houses the C64x+ and other video
+ * hardware such as VICP. In some chips, the "DSP" domain is not always on.
+ * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
  */
 
 /* Works on Always On power domain only (no PD argument) */
@@ -55,15 +55,17 @@ void lpsc_on(unsigned int id)
 	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
 	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
 
-	while (REG(PSC_PTSTAT) & 0x01);
+	while (REG(PSC_PTSTAT) & 0x01)
+		continue;
 
 	if ((*mdstat & 0x1f) == 0x03)
 		return;			/* Already on and enabled */
 
 	*mdctl |= 0x03;
 
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
 	switch (id) {
+#ifdef CONFIG_SOC_DM644X
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
 	case DAVINCI_LPSC_VPSSSLV:
 	case DAVINCI_LPSC_EMAC:
 	case DAVINCI_LPSC_EMAC_WRAPPER:
@@ -80,14 +82,20 @@ void lpsc_on(unsigned int id)
 	case DAVINCI_LPSC_GPIO:
 		*mdctl |= 0x200;
 		break;
+#endif
 	}
 
 	REG(PSC_PTCMD) = 0x01;
 
-	while (REG(PSC_PTSTAT) & 0x03);
-	while ((*mdstat & 0x1f) != 0x03);	/* Probably an overkill... */
+	while (REG(PSC_PTSTAT) & 0x03)
+		continue;
+	while ((*mdstat & 0x1f) != 0x03)	/* Probably an overkill... */
+		continue;
 }
 
+/* Not all DaVinci chips have a DSP power domain. */
+#ifdef CONFIG_SOC_DM644X
+
 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
 #if !defined(CONFIG_SYS_USE_DSPLINK)
 void dsp_on(void)
@@ -124,59 +132,4 @@ void dsp_on(void)
 }
 #endif /* CONFIG_SYS_USE_DSPLINK */
 
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x0000e003;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable EMAC. */
-	REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= PINMUX1_I2C;
-}
-
-void davinci_errata_workarounds(void)
-{
-	/*
-	 * Workaround for TMS320DM6446 errata 1.3.22:
-	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
-	 *   Revision(s) Affected: 1.3 and earlier
-	 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/*
-	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
-	 * as suggested in TMS320DM6446 errata 2.1.2:
-	 *
-	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
-	 * low priority modules can occupy the bus and prevent high priority
-	 * modules like the VPSS from getting the required DDR2 throughput.
-	 * A hex value of 0x20 should provide a good ARM (cache enabled)
-	 * performance and still allow good utilization by the VPSS or other
-	 * modules.
-	 */
-	REG(VBPR) = 0x20;
-}
+#endif /* have a DSP */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 9fe4072..9be10f7 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -59,6 +59,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index a16ac39..d5e77f8 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -34,6 +34,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /*=============*/
 /* Memory Info */
 /*=============*/
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index c2ebd97..4be5b7e 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /* EEPROM definitions for Atmel 24LC64 EEPROM chip */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 0fc6012..a6bf825 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -59,6 +59,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */