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author | Sonic Zhang <sonic.zhang@analog.com> | 2013-02-05 18:57:49 +0800 |
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committer | Sonic Zhang <sonic.zhang@analog.com> | 2013-05-13 15:47:24 +0800 |
commit | f4d8038439fb372c91c3a27121a911c359603bcf (patch) | |
tree | c9a576f2f81d7ad65d8222f20f5c4a1fc4fa0e24 | |
parent | ddb5c5be1eddd38a47dc197cfacdbf149930740d (diff) | |
download | u-boot-imx-f4d8038439fb372c91c3a27121a911c359603bcf.zip u-boot-imx-f4d8038439fb372c91c3a27121a911c359603bcf.tar.gz u-boot-imx-f4d8038439fb372c91c3a27121a911c359603bcf.tar.bz2 |
blackfin: run core1 from L1 code sram start address in uboot init code on core 0
Define core 1 L1 code sram start address.
Add function to enable core 1 for BF609 and BF561.
Add config macro to allow customer to run core 1 in uboot init code on core 0.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
-rw-r--r-- | arch/blackfin/cpu/cpu.c | 30 | ||||
-rw-r--r-- | arch/blackfin/include/asm/mach-bf561/BF561_def.h | 2 | ||||
-rw-r--r-- | arch/blackfin/include/asm/mach-bf609/BF609_def.h | 2 | ||||
-rw-r--r-- | include/configs/bf561-ezkit.h | 5 | ||||
-rw-r--r-- | include/configs/bf609-ezkit.h | 5 |
5 files changed, 44 insertions, 0 deletions
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 0be2e2b..d841f64 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -23,6 +23,32 @@ ulong bfin_poweron_retx; +#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START) +void bfin_core1_start(void) +{ +#ifdef BF561_FAMILY + /* Enable core 1 */ + bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); +#else + /* Enable core 1 */ + bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START); + bfin_write32(RCU0_CRCTL, 0); + + bfin_write32(RCU0_CRCTL, 0x2); + + /* Check if core 1 starts */ + while (!(bfin_read32(RCU0_CRSTAT) & 0x2)) + continue; + + bfin_write32(RCU0_CRCTL, 0); + + /* flag to notify cces core 1 application */ + bfin_write32(SDU0_MSG_SET, (1 << 19)); +#endif +} +#endif + +__attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1 @@ -72,6 +98,10 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) # endif #endif +#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START) + bfin_core1_start(); +#endif + serial_early_puts("Board init flash\n"); board_init_f(bootflag); } diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h index a7ff5a3..8fd552f 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h @@ -714,4 +714,6 @@ #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define COREB_L1_CODE_START 0xFF600000 + #endif /* __BFIN_DEF_ADSP_BF561_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h index 8c1dcd0..4d3b003 100644 --- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h @@ -244,4 +244,6 @@ #define L1_INST_SRAM_SIZE 0x8000 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define COREB_L1_CODE_START 0xFF600000 + #endif /* __BFIN_DEF_ADSP_BF609_proc__ */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 1a9d27e..6ee1e4c 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -98,6 +98,11 @@ */ #define CONFIG_UART_CONSOLE 0 +/* + * Run core 1 from L1 SRAM start address when init uboot on core 0 + */ +/* #define CONFIG_CORE1_RUN 1 */ + /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 02149fa..8b90129 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -156,6 +156,11 @@ #endif /* + * Run core 1 from L1 SRAM start address when init uboot on core 0 + */ +/* #define CONFIG_CORE1_RUN 1 */ + +/* * Pull in common ADI header for remaining command/environment setup */ #include <configs/bfin_adi_common.h> |