diff options
| author | Timur Tabi <timur@freescale.com> | 2007-07-03 13:04:34 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-08-10 01:12:03 -0500 |
| commit | df33f6b4d6d63693dd9200808b242de1b86cb8e8 (patch) | |
| tree | 670295262e8d55ebc544e2e13ccde39ec300aed0 | |
| parent | 9546266999f0b9b51372636614211b88d90f0f25 (diff) | |
| download | u-boot-imx-df33f6b4d6d63693dd9200808b242de1b86cb8e8.zip u-boot-imx-df33f6b4d6d63693dd9200808b242de1b86cb8e8.tar.gz u-boot-imx-df33f6b4d6d63693dd9200808b242de1b86cb8e8.tar.bz2 | |
Update SCCR programming in cpu_init_f() to support all 83xx processors
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors. The code to update some bitfields was
compiled only on some processors. Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| -rw-r--r-- | cpu/mpc83xx/cpu_init.c | 14 | ||||
| -rw-r--r-- | include/mpc83xx.h | 2 |
2 files changed, 14 insertions, 2 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 3ac9161..53a5f59 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -83,20 +83,30 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); #endif -#ifdef CONFIG_MPC834X #ifdef CFG_SCCR_TSEC1CM /* TSEC1 clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); #endif + #ifdef CFG_SCCR_TSEC2CM /* TSEC2 & I2C1 clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); #endif + +#ifdef CFG_SCCR_TSEC1ON + /* TSEC1 clock switch */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); +#endif + +#ifdef CFG_SCCR_TSEC2ON + /* TSEC2 clock switch */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); +#endif + #ifdef CFG_SCCR_USBMPHCM /* USB MPH clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); #endif -#endif /* CONFIG_MPC834X */ #ifdef CFG_SCCR_PCICM /* PCI & DMA clock mode */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 01df06b..829dbf9 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -602,7 +602,9 @@ #define SCCR_TSEC1CM_3 0xC0000000 #define SCCR_TSEC1ON 0x20000000 +#define SCCR_TSEC1ON_SHIFT 29 #define SCCR_TSEC2ON 0x10000000 +#define SCCR_TSEC2ON_SHIFT 28 #endif |