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authorPeng Fan <Peng.Fan@freescale.com>2015-01-29 16:33:11 +0800
committerFrank Li <Frank.Li@freescale.com>2015-02-04 21:53:32 +0800
commitdddb52ebdc6c4919da0103a364563dbe2c100874 (patch)
treeea3177e18c9541153de0f25f2e62e13d6e22f9da
parent71779872ed7072f0ca90dd4db776dd8960b595f4 (diff)
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MLK-10178-10 mtd:nand:mxs fix potential dcache issue
DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
-rw-r--r--drivers/mtd/nand/mxs_nand.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 8ef9b07..a526ba3 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -7,7 +7,7 @@
* Based on code from LTIB:
* Freescale GPMI NFC NAND Flash Driver
*
- * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2008 Embedded Alley Solutions, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -456,6 +456,9 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
mxs_dma_desc_append(channel, d);
+ /* Invalidate caches */
+ mxs_nand_inval_data_buf(nand_info);
+
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret) {
@@ -622,6 +625,9 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
mxs_dma_desc_append(channel, d);
+ /* Invalidate caches */
+ mxs_nand_inval_data_buf(nand_info);
+
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret) {