zynq: Add support for U-BOOT SPL

SPL is using ps7_init.c/h files which are generated
from design tools which have to be copied to
boards/xilinx/zynq folder before compilation.

BSS section is moved to SDRAM because fat support
requires more space than SRAM size.

Added:
- MMC and QSPI support
- Boot OS directly from SPL
- Enable SPL command

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>

8 files changed, 241 insertions, 2 deletions

diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index 3374789..3363a3c 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -13,3 +13,4 @@ obj-y	+= cpu.o
 obj-y	+= ddrc.o
 obj-y	+= slcr.o
 obj-y	+= clk.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 5d505dd..7626b5c 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -17,7 +17,7 @@ void lowlevel_init(void)
 int arch_cpu_init(void)
 {
 	zynq_slcr_unlock();
-
+#ifndef CONFIG_SPL_BUILD
 	/* Device config APB, unlock the PCAP */
 	writel(0x757BDF0D, &devcfg_base->unlock);
 	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
@@ -35,7 +35,7 @@ int arch_cpu_init(void)
 	/* Urgent write, ports S2/S3 */
 	writel(0xC, &slcr_base->ddr_urgent);
 #endif
-
+#endif
 	zynq_clk_early_init();
 	zynq_slcr_lock();
 
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
new file mode 100644
index 0000000..fcad762
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+	ps7_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	preloader_console_init();
+	arch_cpu_init();
+	board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode;
+
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	case ZYNQ_BM_QSPI:
+		puts("qspi boot\n");
+		mode = BOOT_DEVICE_SPI;
+		break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	case ZYNQ_BM_SD:
+		puts("mmc boot\n");
+		mode = BOOT_DEVICE_MMC1;
+		break;
+#endif
+	default:
+		puts("Unsupported boot mode selected\n");
+		hang();
+	}
+
+	return mode;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+	return MMCSD_MODE_FAT;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* boot linux */
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
new file mode 100644
index 0000000..0c4501e
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014 Xilinx, Inc. Michal Simek
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		__image_copy_start = .;
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	} > .sram
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .sram
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	} > .sram
+
+	. = ALIGN(4);
+
+	. = .;
+
+	__image_copy_end = .;
+
+	_end = .;
+
+	/* Move BSS section to RAM because of FAT */
+	.bss (NOLOAD) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		__bss_end = .;
+	} > .sdram
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/include/asm/arch-zynq/spl.h b/arch/arm/include/asm/arch-zynq/spl.h
new file mode 100644
index 0000000..5789d28
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/spl.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+extern void ps7_init(void);
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_RAM		1
+#define BOOT_DEVICE_SPI		2
+#define BOOT_DEVICE_MMC1	3
+#define BOOT_DEVICE_MMC2	4
+#define BOOT_DEVICE_MMC2_2	5
+
+#endif
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 6301a8c..3f19a1c 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -6,3 +6,4 @@
 #
 
 obj-y	:= board.o
+obj-$(CONFIG_SPL_BUILD)	+= ps7_init.o
diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c
new file mode 100644
index 0000000..c47da09
--- /dev/null
+++ b/board/xilinx/zynq/ps7_init.c
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/spl.h>
+
+__weak void ps7_init(void)
+{
+	puts("Please copy ps7_init.c/h from hw project\n");
+}
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index d6dc745..c7eee0a 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -228,4 +228,81 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_TFTPPUT
 
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
+
+/* Disable dcache for SPL just for sure */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_FPGA
+#endif
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI0
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot.img"
+#endif
+
+/* Address in RAM where the parameters must be copied by SPL. */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x10000000
+
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"system.dtb"
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
+
+/* Not using MMC raw mode - just for compilation purpose */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0
+
+/* qspi mode is working fine */
+#ifdef CONFIG_ZYNQ_QSPI
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS	0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
+#define CONFIG_SPL_SPI_CS	0
+#endif
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SPL_TEXT_BASE	0x0
+
+/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
+#define CONFIG_SPL_MAX_SIZE	0x30000
+
+/* The highest 64k OCM address */
+#define OCM_HIGH_ADDR	0xffff0000
+
+/* Just define any reasonable size */
+#define CONFIG_SPL_STACK_SIZE	0x1000
+
+/* SPL stack position - and stack goes down */
+#define CONFIG_SPL_STACK	(OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
+
+/* On the top of OCM space */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_STACK + \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x1000
+
+/* BSS setup */
+#define CONFIG_SPL_BSS_START_ADDR	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+
 #endif /* __CONFIG_ZYNQ_COMMON_H */