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author | Simon Glass <sjg@chromium.org> | 2015-03-26 09:29:38 -0600 |
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committer | Simon Glass <sjg@chromium.org> | 2015-04-18 11:11:16 -0600 |
commit | ce6adaa4b5b51ddf7dc53d61c1eca0fc0553ac06 (patch) | |
tree | a155bc0ccb17eccb27a7e02397d59de2eb46a572 | |
parent | 672055e20b78c2de1f1309b883d9718cdf5ba5f9 (diff) | |
download | u-boot-imx-ce6adaa4b5b51ddf7dc53d61c1eca0fc0553ac06.zip u-boot-imx-ce6adaa4b5b51ddf7dc53d61c1eca0fc0553ac06.tar.gz u-boot-imx-ce6adaa4b5b51ddf7dc53d61c1eca0fc0553ac06.tar.bz2 |
fdt: Drop LPC compatible string in fdtdec
This is not needed now that we have moved chromebook_link and cros_ec to
driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
-rw-r--r-- | include/fdtdec.h | 1 | ||||
-rw-r--r-- | lib/fdtdec.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/include/fdtdec.h b/include/fdtdec.h index e30adbd..c038fa8 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -158,7 +158,6 @@ enum fdt_compat_id { COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ - COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_MEMORY_SPD, /* Memory SPD information */ COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index f87dc3f..9ed610e 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,7 +66,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(PARADE_PS8625, "parade,ps8625"), - COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x-lpc"), COMPAT(INTEL_MICROCODE, "intel,microcode"), COMPAT(MEMORY_SPD, "memory-spd"), COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"), |