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authorValentin Longchamp <valentin.longchamp@keymile.com>2012-07-05 05:05:07 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:37 +0200
commitc1b8514a7a94b6b7e4e2bd779ecda16c86248299 (patch)
tree406c19cde3de3f37c298c01de910017f7ac9bb40
parent48ced62cfb1722c97b6e598036b4e204980c4c47 (diff)
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arm/km: redefine piggy 4 reg names to avoid conflicts
Some very similar #defines for reg addresses are used in a later patch (managed_switch support for km_arm). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
-rw-r--r--board/keymile/km_arm/km_arm.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index c8da823..ed2454f 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -328,13 +328,13 @@ void dram_init_banksize(void)
#if (defined(CONFIG_KM_PIGGY4_88E6061))
-#define PHY_LED_SEL 0x18
-#define PHY_LED0_LINK (0x5)
-#define PHY_LED1_ACT (0x8<<4)
-#define PHY_LED2_INT (0xe<<8)
-#define PHY_SPEC_CTRL 0x1c
+#define PHY_LED_SEL_REG 0x18
+#define PHY_LED0_LINK (0x5)
+#define PHY_LED1_ACT (0x8<<4)
+#define PHY_LED2_INT (0xe<<8)
+#define PHY_SPEC_CTRL_REG 0x1c
#define PHY_RGMII_CLK_STABLE (0x1<<10)
-#define PHY_CLSA (0x1<<1)
+#define PHY_CLSA (0x1<<1)
/* Configure and enable MV88E3018 PHY */
void reset_phy(void)
@@ -346,15 +346,15 @@ void reset_phy(void)
return;
/* RGMII clk transition on data stable */
- if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0)
+ if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
printf("Error reading PHY spec ctrl reg\n");
- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
- reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
+ if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+ reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
printf("Error writing PHY spec ctrl reg\n");
/* leds setup */
- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
- PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
+ if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+ PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
printf("Error writing PHY LED reg\n");
/* reset the phy */