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author | Simon Glass <sjg@chromium.org> | 2014-11-10 17:16:50 -0700 |
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committer | Simon Glass <sjg@chromium.org> | 2014-11-21 08:14:02 +0100 |
commit | bc0b28427a12682f99dcf368a6d58f1f9bf58cd0 (patch) | |
tree | ec0eb58eb8b32c590f653cd4979617170e86346c | |
parent | a94f468fa292c43be7ac9fe35adea5065fbc2a28 (diff) | |
download | u-boot-imx-bc0b28427a12682f99dcf368a6d58f1f9bf58cd0.zip u-boot-imx-bc0b28427a12682f99dcf368a6d58f1f9bf58cd0.tar.gz u-boot-imx-bc0b28427a12682f99dcf368a6d58f1f9bf58cd0.tar.bz2 |
dm: tegra: Add platform data for the SPL uart
Since we currently don't have device tree available in SPL, add platform
data so the uart works.
Signed-off-by: Simon Glass <sjg@chromium.org>
-rw-r--r-- | drivers/serial/serial_tegra.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c index 7eb70e1..b9227f0 100644 --- a/drivers/serial/serial_tegra.c +++ b/drivers/serial/serial_tegra.c @@ -9,6 +9,7 @@ #include <ns16550.h> #include <serial.h> +#ifdef CONFIG_OF_CONTROL static const struct udevice_id tegra_serial_ids[] = { { .compatible = "nvidia,tegra20-uart" }, { } @@ -26,13 +27,28 @@ static int tegra_serial_ofdata_to_platdata(struct udevice *dev) return 0; } +#else +struct ns16550_platdata tegra_serial = { + .base = CONFIG_SYS_NS16550_COM1, + .reg_shift = 2, + .clock = V_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_serial) = { + "serial_tegra20", &tegra_serial +}; +#endif + U_BOOT_DRIVER(serial_ns16550) = { .name = "serial_tegra20", .id = UCLASS_SERIAL, +#ifdef CONFIG_OF_CONTROL .of_match = tegra_serial_ids, .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, }; |