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authorYe Li <ye.li@nxp.com>2017-03-06 21:35:08 +0800
committerYe Li <ye.li@nxp.com>2017-04-05 14:04:43 +0800
commitb9c64d0ef3f10a07b6140555353a063c166f2f8f (patch)
treea49dd55dc38651907e55aaa67f4f2b0e584f9817
parent70bc3dd2c40a5c5479b4aae6037e7914061a524e (diff)
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MLK-14363 mx6qsabreauto: Fix ethernet PHY setting issue
The PHY settings for RGMII has been removed from mx6qsabreauto board codes, due to the atheros PHY driver have updated to use same configuration for AR8031 and AR8035, while this configuration is duplicated as we set in board codes. But in recent codes, the PHY driver added a patch for AR8031 independent config. So needs to add the PHY settings back to the board codes. Signed-off-by: Ye Li <ye.li@nxp.com>
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 2c7b096..04c8f8d 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -447,6 +447,39 @@ static void setup_gpmi_nand(void)
}
#endif
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
static void setup_fec(void)
{
int ret;