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authorRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>2013-09-27 16:52:57 +0530
committerMichal Simek <michal.simek@xilinx.com>2013-11-06 09:24:06 +0100
commitb5f05b063413245e3d29186739fb5db98d137dfd (patch)
treec039aa98f4efd1884c035d49a61edcd13699f753
parentc1824ea268b1a565fd6956d79a91e4460d88a88b (diff)
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arm: zynq : Revert TZ_DDR_RAM to secure.
TZ_DDR_RAM on reset is in secure mode. Since uboot and linux runs in full TZ privilege secure mode, no need to set DDR trustzone to non-secure. Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--arch/arm/cpu/armv7/zynq/cpu.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 0ca5d8a..9af340e 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -29,8 +29,6 @@ int arch_cpu_init(void)
writel(0x1F, &slcr_base->ocm_cfg);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
writel(0x0, &slcr_base->fpga_rst_ctrl);
- /* TZ_DDR_RAM, Set DDR trust zone non-secure */
- writel(0xFFFFFFFF, &slcr_base->trust_zone);
/* Set urgent bits with register */
writel(0x0, &slcr_base->ddr_urgent_sel);
/* Urgent write, ports S2/S3 */