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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2015-03-11 17:12:12 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-05-15 19:21:24 +0200 |
| commit | b4ed9f86df441d7ac304f70cc711c257e7c8ebf1 (patch) | |
| tree | f4d7cb36366971a6397f1cc5ec0ee8217c196655 | |
| parent | 9927d60f4aadcecbd3143400d01ad4500438ea4f (diff) | |
| download | u-boot-imx-b4ed9f86df441d7ac304f70cc711c257e7c8ebf1.zip u-boot-imx-b4ed9f86df441d7ac304f70cc711c257e7c8ebf1.tar.gz u-boot-imx-b4ed9f86df441d7ac304f70cc711c257e7c8ebf1.tar.bz2 | |
mx6: Set shared override bit in PL310 AUX_CTRL register
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/pl310.h | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dd34138..21ef9d0 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -523,6 +523,14 @@ void v7_outer_cache_enable(void) struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; unsigned int val; + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); + #if defined CONFIG_MX6SL struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; val = readl(&iomux->gpr[11]); diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index ddc245b..de7650e 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -16,6 +16,8 @@ #define L2X0_STNDBY_MODE_EN (1 << 0) #define L2X0_CTRL_EN 1 +#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type; |