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| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2013-01-30 11:19:15 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-02-12 13:52:30 +0100 |
| commit | ada02b84636242f5142f74016dbedb50889e93d0 (patch) | |
| tree | 4468b2a516e6337b5fe0fc80ab53a1a3eeb4dcd8 | |
| parent | aa53149e1108ab9395ee8309ce6f90480bfdf34b (diff) | |
| download | u-boot-imx-ada02b84636242f5142f74016dbedb50889e93d0.zip u-boot-imx-ada02b84636242f5142f74016dbedb50889e93d0.tar.gz u-boot-imx-ada02b84636242f5142f74016dbedb50889e93d0.tar.bz2 | |
imx: mx6q DDR3 init: Fix SDE_to_RST
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| -rw-r--r-- | board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 1c24da8..73317b5 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005A0E21 +DATA 4 0x021b0030 0x005A1021 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 |