diff options
| author | Lei Wen <[leiwen@marvell.com]> | 2011-11-01 16:25:56 +0530 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-11-03 22:56:22 +0100 |
| commit | abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456 (patch) | |
| tree | b591517ea82849ff240017312972bfc0daf3fe42 | |
| parent | 0caac5f4155a1db6c5ce921c7f9294b6b46e7744 (diff) | |
| download | u-boot-imx-abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456.zip u-boot-imx-abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456.tar.gz u-boot-imx-abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456.tar.bz2 | |
armada100: define CONFIG_SYS_CACHELINE_SIZE
By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long
Signed-off-by: Lei Wen <leiwen@marvell.com>
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/config.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index d2094e5..637f313 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -33,6 +33,8 @@ #include <asm/arch/armada100.h> #define CONFIG_ARM926EJS 1 /* Basic Architecture */ +/* default Dcache Line length for armada100 */ +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ |