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authorMike Dunn <mikedunn@newsguy.com>2013-06-21 09:12:28 -0700
committerMarek Vasut <marex@denx.de>2013-06-22 15:25:28 +0200
commit9dc8fef2583f23ca6a99c6f5e709a8b80018364f (patch)
tree7bcd2987166a8f966dcfc4e4610376d7f061ea36
parent84c617beb2ddcda03e36abe553432e2784ada6b7 (diff)
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pxa: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained after writing code over the data bus, even if the caches are disabled. Tested on the pxa270. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
-rw-r--r--arch/arm/lib/relocate.S9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 949b9e8..cd2bab6 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -70,6 +70,15 @@ fixnext:
relocate_done:
+#ifdef __XSCALE__
+ /*
+ * On xscale, icache must be invalidated and write buffers drained,
+ * even with cache disabled - 4.2.7 of xscale core developer's manual
+ */
+ mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
+ mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+#endif
+
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__