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| author | Hans de Goede <hdegoede@redhat.com> | 2014-11-09 12:24:55 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2014-11-25 13:38:46 +0100 |
| commit | 9d4b7d0bc83992277d4baad16bdc19624f28c51c (patch) | |
| tree | c69feb004399c42276d10f063d92817ab4a1e8d7 | |
| parent | 2a82ec77d27ef5f860a107c4b764643a655dceeb (diff) | |
| download | u-boot-imx-9d4b7d0bc83992277d4baad16bdc19624f28c51c.zip u-boot-imx-9d4b7d0bc83992277d4baad16bdc19624f28c51c.tar.gz u-boot-imx-9d4b7d0bc83992277d4baad16bdc19624f28c51c.tar.bz2 | |
sun4i: Rename dram_clk_cfg to dram_clk_gate
The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so name it the same on sun4i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun4i.c | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index dc9fdb9..ec8aaa7 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -428,9 +428,9 @@ static void dramc_clock_output_en(u32 on) #ifdef CONFIG_MACH_SUN4I struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; if (on) - setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); else - clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); #endif } diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 9dca800..6c0430c 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -62,7 +62,7 @@ struct sunxi_ccm_reg { u32 gps_clk_cfg; /* 0xd0 */ u32 spi3_clk_cfg; /* 0xd4 */ u8 res5[0x28]; - u32 dram_clk_cfg; /* 0x100 */ + u32 dram_clk_gate; /* 0x100 */ u32 be0_clk_cfg; /* 0x104 */ u32 be1_clk_cfg; /* 0x108 */ u32 fe0_clk_cfg; /* 0x10c */ |