diff options
| author | TsiChung Liew <Tsi-Chung.Liew@freescale.com> | 2009-03-02 19:16:45 +0000 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2009-03-17 15:58:37 -0600 |
| commit | 9017d9325a5067b2ab0d70a2d3c907620c9ab7f8 (patch) | |
| tree | c97754e224acfe4d9ada80a0b6005b6ef8b9aed1 | |
| parent | 42b68af1062f75bb4a91cf47e329a7e8100cd815 (diff) | |
| download | u-boot-imx-9017d9325a5067b2ab0d70a2d3c907620c9ab7f8.zip u-boot-imx-9017d9325a5067b2ab0d70a2d3c907620c9ab7f8.tar.gz u-boot-imx-9017d9325a5067b2ab0d70a2d3c907620c9ab7f8.tar.bz2 | |
ColdFire: Fix M5329EVB and M5373EVB nand issue
The Nand flash was unable to read and write properly
due to Nand Chip Select (nCE) setup was in reverse
order. Also, increase the Nand time out value to 60.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| -rw-r--r-- | board/freescale/m5329evb/nand.c | 6 | ||||
| -rw-r--r-- | board/freescale/m5373evb/nand.c | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index cf27dda..16025f9 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -47,10 +47,12 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; IO_ADDR_W &= ~(SET_ALE | SET_CLE); - *nCE &= 0xFFFB; if (ctrl & NAND_NCE) + *nCE &= 0xFFFB; + else *nCE |= 0x0004; + if (ctrl & NAND_CLE) IO_ADDR_W |= SET_CLE; if (ctrl & NAND_ALE) @@ -78,7 +80,7 @@ int board_nand_init(struct nand_chip *nand) gpio->pclrr_timer = 0; gpio->podr_timer = 0; - nand->chip_delay = 50; + nand->chip_delay = 60; nand->ecc.mode = NAND_ECC_SOFT; nand->cmd_ctrl = nand_hwcontrol; diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index 3ebef05..df8c03b 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -47,10 +47,12 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; IO_ADDR_W &= ~(SET_ALE | SET_CLE); - *nCE &= 0xFFFB; if (ctrl & NAND_NCE) + *nCE &= 0xFFFB; + else *nCE |= 0x0004; + if (ctrl & NAND_CLE) IO_ADDR_W |= SET_CLE; if (ctrl & NAND_ALE) @@ -82,7 +84,7 @@ int board_nand_init(struct nand_chip *nand) gpio->pclrr_timer = 0; gpio->podr_timer = 0; - nand->chip_delay = 50; + nand->chip_delay = 60; nand->ecc.mode = NAND_ECC_SOFT; nand->cmd_ctrl = nand_hwcontrol; |