diff options
| author | Jon Loeliger <jdl@freescale.com> | 2007-08-13 11:01:52 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2007-08-13 11:01:52 -0500 |
| commit | 8e2dd87eee01bb1b83beab7caf22b851c5cafb2c (patch) | |
| tree | 47a43e05d90de7d64ed356bab5f15e8d89f5b5cc | |
| parent | cca34967cbd13ff6bd352be29e3f1cc88ab24c05 (diff) | |
| parent | 9986bc3e40e899bea372a99a2bca4071bdf2e24b (diff) | |
| download | u-boot-imx-8e2dd87eee01bb1b83beab7caf22b851c5cafb2c.zip u-boot-imx-8e2dd87eee01bb1b83beab7caf22b851c5cafb2c.tar.gz u-boot-imx-8e2dd87eee01bb1b83beab7caf22b851c5cafb2c.tar.bz2 | |
Merge commit 'remotes/wd/master'
Conflicts:
MAKEALL
With any luck, this is the last MAKEALL merge conflict!
78 files changed, 7772 insertions, 841 deletions
@@ -1,3 +1,756 @@ +commit 77d19a8bf3b0b1e401cb9f23c81e2ef419705c1a +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Aug 12 21:34:34 2007 +0200 + + Minor alignment of output, 2nd try. + Also update CHANGELOG + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 6b309f22a724fad8418e811751a0741b893419cf +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Aug 12 20:35:49 2007 +0200 + + Minor alignment of output + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 6f6d7b9c8559e241e8d232621542b8b59699b07b +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Aug 12 18:28:18 2007 +0200 + + Cleanup output on ADS5121 board + + Signed-off-by: Wolfgang Denk + +commit a4d2636f2a859245ed3a401f26189da2dfda4ceb +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Aug 12 15:11:38 2007 +0200 + + Adapt board configuration and fix kernel crash on MCC200 board. + + The update procedure was modified to turn off the USB subsystem + before exit for MCC200 and TRAB. This is necessary as otherwise the + USB controller continues to write periodically to system memory! + + MCC200-specific notes: + - the patch disables the magic key check for MCC200 + - the patch contains the configuration changes made + for the new revision of the board. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit e27f3a6efb9db5a533223b05c629ff4ac8d921bf +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Aug 12 14:47:54 2007 +0200 + + Adjust default configuration of ADS5121 board. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit afaac86fe2948ac84cd9a12bbed883b3c683e7d9 +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Aug 12 14:27:39 2007 +0200 + + Clean up some remaining CFG_CMD_ -> CONFIG_CMD_ issues. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 5fe6be6208dda852c3564e384bd78d75784dea3e +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Tue Aug 7 21:14:22 2007 -0400 + + Improve error print messages. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 99dffca3b7590a16a00bc475c860b67b2a3f1462 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jul 17 13:57:04 2007 -0500 + + fdt: allow for builds that don't want env and bd_t nodes + + protect fdt_env and fdt_bd_t invocations, fix codingstyle while in the + area. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 91148bf7aeba142d6f348805db7625db7da64d6f +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jul 17 13:56:53 2007 -0500 + + fdt: do board setup based on fdt address specified on bootm line + + The last fdt patch to bootm did board setup based on the address + specified by a prior fdt address command invocation. The bootm + code, as its call to fdt_chosen does, should use the fdt specified + by the user on the bootm command. Note this restores full + functionality for the 8360's existing default boot environment + values, e.g. 'run nfsboot' (i.e. no having to 'fdt addr $fdtaddr' + before booting a kernel). + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit e125a2ffc209dd34794e326c7175658253beadf3 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Tue Jul 10 20:40:39 2007 -0400 + + Call ft_board_setup() from the bootm command. + + In the patch titled "Create new fdt boardsetup command..." I removed the + call to ft_board_setup() from the routine fdt_chosen(), but I forgot + to add a direct call back into cmd_bootm.c + + This fixes the oversight by adding the direct call to the bootm command. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit fd61e55dd8cb52ce3ff91b3917af26e24b6b0845 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Mon Jun 25 23:25:28 2007 -0400 + + Create new fdt boardsetup command, fix bug parsing [] form of set values. + + Previously ft_board_setup() was called by fdt_chosen() which was not + really correctly structured. This splits ft_board_setup() out by creating + a new fdt boardsetup command. + + Fix a bug when parsing fdt set command values which have the square + bracket form [00 11 22 33] - the length was updated incorrectly in when + parsing that form. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 6f35ded9e85493595e0eb66a82b502a95326d049 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Mon Jun 25 20:55:58 2007 -0400 + + Tighten up the error messages. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit c45874b05aae897a6c29d1a97d4bb708fca2756c +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Mon Jun 25 19:52:23 2007 -0400 + + Asthetic improvements: error messages and line lengths. + + Tighten up the error messages, split overlength lines. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 35ec398f16e17df600edc1b38c1e9e62c15c9aa1 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Fri May 25 22:08:57 2007 -0400 + + Fix fdt_chosen() to call ft_board_setup(), clean up long lines. + + The fdt_chosen() function was adding/seting some properties ad-hoc + improperly and duplicated (poorly) what was done in ft_board_setup() + + Clean up long lines (setting properties, printing errors). + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 06e19a07701c968f15d72c083b5872a1a11c7b01 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Mon May 21 23:27:16 2007 -0400 + + For fdt_find_node_by_path(), handle the root path properly. + + Also removes the special case root path detection in cmd_fdt.c since it + is no longer necessary. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 9675ee7208ab965d13ea8d8262d77ac4160ef549 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Thu May 17 23:54:36 2007 -0400 + + Add fdt_find_node_by_type() and fdt_find_compatible_node() to LIBFDT + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Acked-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 1a861169bc3758f9de3aead62b058736c6891246 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Wed Jun 6 22:47:58 2007 -0400 + + Replace fdt_node_offset() with fdt_find_node_by_path(). + + The new name matches more closely the kernel's name, which is also + a much better description. + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Acked-by: Gerald Van Baren <vanbaren@cideas.com> + +commit addd8ce83078c25f0eca5f23adbdfc64ca50a243 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Wed May 16 22:39:59 2007 -0400 + + Fix cmd_fdt line lengths, refactor code. + + Break lines that were greater than 80 characters in length. + Move the fdt print and property parsing code to separate static functions + to reduce coding clutter in the fdt_cmd handling body. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 25114033ab21788810c48ba4df103b649da1223b +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Sat May 12 09:47:25 2007 -0400 + + FDT command improvements. + + Fix "fdt set" so that it will create a non-existing property. + Add "fdt mknode" to create nodes. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 38eb508e8e811e2e57628f445de3a24a23c7d804 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Sat May 12 09:45:46 2007 -0400 + + Reorganize and fix problems (returns) in the bootm command. + + Do *NOT* return after the "point of no return" has been passed. + If something goes wrong, the board must be reset after that point. + Move the "Transferring control to Linux" debug message back to where it + belongs: just before transferring control to linux. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 89c8757d8f213c47709bdc4efe0695263a6080a6 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Tue May 8 21:27:35 2007 -0400 + + Fix bugs in the CONFIG_OF_LIBFDT + + Stupid coding mistakes (identified by Timur Tabi, thanks). + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 6be07cc1ca458278c85ecdbf1a0536cff4c701ec +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Wed Apr 25 22:47:15 2007 -0400 + + Improve fdt move length handling. + + Make the length parameter optional: if not specified, do the move using + the current size unchanged. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit bb930e76fea6cf89ca2d98e2f7c7a6043d79327d +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Wed Apr 25 22:23:36 2007 -0400 + + Minor code clean up. + + Declare the variable fdt properly as extern. + Call the "set_fn" function pointer the "short way" without the full + dereferencing syntax. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit ba24e2ac3bdb5c489f3c787e7542b6474c4d65c6 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Wed Apr 25 21:24:27 2007 -0400 + + Improve error messages, more informative. + + Print more than the raw libfdt error message strings. This is especially + useful for cluing in the user when the bootm command aborts due to + blob problems. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 8096b3b8f772c1894ddeda9dbceff6a8826473a4 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Fri Apr 20 22:46:53 2007 -0400 + + libfdt: Conditionally compile based on CONFIG_OF_LIBFDT + + This is the way u-boot reduces configured-out code. At Wolfgang + Grandegger and Wolfgang Denk's request, make libfdt conform. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 923efd286411ed052d9e074f59f8986d6081061c +Author: Bruce Adler <bruce.adler@ccpu.com> +Date: Fri Aug 10 14:54:47 2007 -0700 + + add image size and descriptors for Spartan 3E FPGA chips + + Spartan 3E image sizes taken from Table 1-4 in Xilinx UG332 (v1.1) + + Signed-off by: Bruce Adler <bruce.adler@ccpu.com> + +commit fb56579ffe7ef3275b7036bb7b924e5a0d32bd70 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Fri Aug 10 15:34:48 2007 -0500 + + make MAKEALL more immune to merge conflicts + + ..by placing board entries one per line, as suggested by jdl. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 2628114ec564f969f34b5f7105fbd168cb8c9c3f +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Fri Aug 10 13:28:25 2007 -0500 + + README: Remove outdated cpu type, board type, and NAME_config lists + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 49bb59912d21aacb507eb81fd21fb7af650c706c +Author: Dave Liu <r63238@freescale.com> +Date: Fri Aug 10 15:48:59 2007 +0800 + + mpc83xx: Suppress the warning 'burstlen' + + suppress the warning 'burstlen' of spd_sdram. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit c2c0ab4aff86622b837a48a0e560351f9afafb95 +Author: Stefan Roese <sr@denx.de> +Date: Fri Aug 10 20:34:58 2007 +0200 + + Conding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c74b2108e31fe09bd1c5d291c3cf360510d4f13e +Author: Sergey Kubushyn <ksi@koi8.net> +Date: Fri Aug 10 20:26:18 2007 +0200 + + [ARM] TI DaVinci support, hopefully final + + Add support for the following DaVinci boards: + - DV_EVM + - SCHMOOGIE + - SONATA + + Changes: + + - Split into separate board directories + - Removed changes to MTD_DEBUG (or whatever it's called) + - New CONFIG_CMD party line followed + - Some cosmetic fixes, cleanup etc. + - Patches against the latest U-Boot tree as of now. + - Fixed CONFIG_CMD_NET in net files. + - Fixed CONFIG_CMD_EEPROM for schmoogie. + - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and + DV_EVM. Can't check if it works on SONATA, don't have a board any more, + but it at least compiles. + + Here is an excerpt from session log on SCHMOOGIE... + + U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) + + DRAM: 128 MB + NAND: 128 MiB + In: serial + Out: serial + Err: serial + ARM Clock : 297MHz + DDR Clock : 162MHz + ETH PHY : DP83848 @ 0x01 + U-Boot > iprobe + Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F + U-Boot > ping 192.168.253.10 + host 192.168.253.10 is alive + U-Boot > + + Signed-off-by: Sergey Kubushyn <ksi@koi8.net> + Acked-by: Dirk Behme <dirk.behme@gmail.com> + Acked-by: Zach Sadecki <Zach.Sadecki@ripcode.com> + Acked-by: Stefan Roese <sr@denx.de> + +commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f +Author: Dirk Behme <dirk.behme@googlemail.com> +Date: Thu Aug 2 17:42:08 2007 +0200 + + Make use of generic 64bit division in nand_util.c + + Use generic 64bit division in nand_util.c. This makes nand_util.c + independent of any toolchain 64bit division. + + Signed-off-by: Dirk Behme <dirk.behme@gmail.com> + +commit f7c086e94e8ce9aad7268af97f73aa6884686f27 +Author: Dirk Behme <dirk.behme@googlemail.com> +Date: Thu Aug 2 17:41:14 2007 +0200 + + Move 64bit division from avr32 to generic lib + + Move the 64bit division from lib_avr32 to lib_generic. With this, all + boards can do_div/__div64_32 if needed, not only avr one. Code is put + to lib_generic, so no larger memory footprint if not used. No code + modifications. Thanks for proposal by Håvard Skinnemoen. + + Signed-off-by: Dirk Behme <dirk.behme@gmail.com> + +commit 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Mon Aug 6 18:18:34 2007 -0500 + + mpc83xx: fix ITX[GP] O=builddir builds + + make: *** No rule to make target `/work/wd/tmp/board/mpc8349itx/u-boot.lds', needed by `/work/wd/tmp/u-boot'. Stop. + + Both the ITX and ITX-GP fail when you use "make O=<some dir> ..." or + "BUILD_DIR=<some dir> ./MAKEALL ..." + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 47e8bc846759e037b8af0e5f9c9f9cfa7a1050c3 +Author: Dave Liu <r63238@freescale.com> +Date: Wed Aug 1 15:00:59 2007 +0800 + + mpc83xx: Correct the README for DDR ECC + + Update the README for DDR ECC, change the name + to README.mpc83xx.ddrecc. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit daab8c67d2defef73dc26ab07f0c3afd1b05d019 +Author: Dave Liu <r63238@freescale.com> +Date: Wed Aug 1 15:00:15 2007 +0800 + + mpc83xx: Consolidate the ECC support of 83xx + + Remove the duplicated source code of ecc command on the <board>.c, + for reused, move these code to cpu/mpc83xx directory. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 036575c544cf1b69654d8fb334bda69c6ff3da36 +Author: Dave Liu <r63238@freescale.com> +Date: Sat Aug 4 13:37:39 2007 +0800 + + mpc83xx: Correct the burst length for DDR2 with 32 bits + + The burst length should be 4 for DDR2 with 32 bits bus + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit 1c274c4e05b6dc9b24edc8aa618b02f607ee6eed +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Jul 25 19:25:33 2007 -0500 + + mpc83xx: add support for the MPC8323E RDB + + MPC8323E based board with 64MB fixed SDRAM, 16MB flash, + five 10/100 ethernet ports connected via an ICPlus IP175C + switch, one PCI slot, and serial. Features not supported + in this patch are SD card interface, 2 USB ports, and the + two phone ports. + + Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 343d91009d55fc5b3ff8cc940597af6c6aa1d359 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Jul 25 19:25:28 2007 -0500 + + mpc83xx: fixup generic pci for libfdt + + add libfdt support to the generic 83xx pci code + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit f57ac7a7b37109245b69db80839ebee26179966a +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Jul 25 19:25:22 2007 -0500 + + mpc83xx: fix 8360 and cpu functions to update fdt being passed + + ..and not the global fdt. Rename local fdt vars to blob so as not to + be confused with the global var with the same three-letter name. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 8be404459a6b7395415a57bb35e8377e3b2b5acb +Author: Jerry Van Baren <gvb.uboot@gmail.com> +Date: Wed Jul 4 21:34:24 2007 -0400 + + mpc83xx: Fix errors when CONFIG_OF_LIBFDT is enabled + + Several node strings were not correct (trailing slashes and properties + in the strings) + Added setting of the timebase-frequency. + Improved error messages and use debug() instead of printf(). + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 26d02c9bbac1751c5e19294f000100b48d43a920 +Author: Jerry Van Baren <gvb.uboot@gmail.com> +Date: Wed Jul 4 21:27:30 2007 -0400 + + mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path(). + + The new name matches more closely the kernel's name, which is also + a much better description. + + These are the mpc83xx changes made necessary by the function name change. + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Acked-by: Gerald Van Baren <vanbaren@cideas.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 9be39a67c9f8fef7107f5df09d673005f04d0963 +Author: Dave Liu <daveliu@freescale.com> +Date: Mon Jun 25 10:41:56 2007 +0800 + + mpc83xx: Add support for the display of reset status + + 83xx processor family has many reset sources, such as + power on reset, software hard reset, software soft reset, + JTAG, bus monitor, software watchdog, check stop reset, + external hard reset, external software reset. + sometimes, to figure out the fault of system, we need to + know the cause of reset early before the prompt of + u-boot present. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit ff9658d7049bf8c8e8e0a05dbe5e9f7e91aa5a5d +Author: Dave Liu <daveliu@freescale.com> +Date: Mon Jun 25 10:41:04 2007 +0800 + + mpc83xx: Fix the align bug of SDMA buffer + + According to the latest user manual, the SDMA temporary + buffer base address must be 4KB aligned. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 66dc2c2dc51f8b88bb8e231bc80cd92eae1d6476 +Author: Dave Liu <daveliu@freescale.com> +Date: Mon Jun 25 13:21:12 2007 +0800 + + mpc83xx: Revise the MPC8360EMDS readme doc + + When the rev2.x silicon mount on the MPC8360EMDS baord, + and if you are using the u-boot version after the commit + 3fc0bd159103b536e1c54c6f4457a09b3aba66ca. + to make the ethernet interface usable, we have to setup + the jumpers correctly. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit e739bc95797aac4fefc4c75b55c7c78e59d3ea9c +Author: Timur Tabi <timur@freescale.com> +Date: Tue Jul 3 13:46:32 2007 -0500 + + FSL I2C driver programs the two I2C busses differently + + The i2c_init() function in fsl_i2c.c programs the two I2C busses differently. + The second I2C bus has its slave address programmed incorrectly and is + missing a 5-us delay. + + Signed-off-by: Timur Tabi <timur@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit df33f6b4d6d63693dd9200808b242de1b86cb8e8 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Jul 3 13:04:34 2007 -0500 + + Update SCCR programming in cpu_init_f() to support all 83xx processors + + Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the + bitfields for all 83xx processors. The code to update some bitfields was + compiled only on some processors. Now, the bitfields are programmed as long + as the corresponding CFG_SCCR option is defined in the board header file. + This means that the board header file should not define any CFG_SCCR macros + for bitfields that don't exist on that processor, otherwise the SCCR will be + programmed incorrectly. + + Signed-off-by: Timur Tabi <timur@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 9546266999f0b9b51372636614211b88d90f0f25 +Author: Martin Krause <martin.krause@tqs.de> +Date: Fri Jun 22 13:04:22 2007 +0200 + + TQM834x: cleanup configuraton + + Remove irritating #undef DEBUG + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 5d497e6bf0f5bf63729b4a47b3fd786d3c77a1bc +Author: david.saada <David.Saada@ecitele.com> +Date: Mon Jun 18 09:09:53 2007 -0700 + + MPC83xx: Fix makefile to generate config.h file in the build directory + + MPC83xx: Fix the Makefile config sections to generate the include/config.h + file in the build directory instead of the source directory. + + Signed-off-by: David Saada <david.saada@ecitele.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 1ded0242e437259366792d52b7e9d1e1931d8fa5 +Author: Lee Nipper <Lee.Nipper@freescale.com> +Date: Thu Jun 14 20:07:33 2007 -0500 + + mpc83xx: Add support for 8360 silicon revision 2.1 + + This change adds 8360 silicon revision 2.1 support to u-boot. + + Signed-off-by: Lee Nipper <lee.nipper@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit a22806469a8f2b69c829f4fd5361fdebd0cb01b4 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Aug 8 04:14:28 2007 -0500 + + Treat ppc64 host as ppc + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 0dc4279b08ff82472bec2e2c90858602459febe8 +Author: Jason Jin <Jason.jin@freescale.com> +Date: Wed Aug 8 09:01:46 2007 +0800 + + Minor fix for bios emulator makefile + + Add $(obj) to LIB avoiding objects be built in the source dir + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit ce981dc857adfc8036ca2f6d5d5a06c2a8aa77d6 +Author: Jason Jin <Jason.jin@freescale.com> +Date: Wed Aug 8 08:33:11 2007 +0800 + + Add CONFIG_BIOSEMU define to guard all the bios emulator code + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + + This patch fix the compile issue on the board that did not enable the bios emulator + +commit ed8106433522f2ea8933e9808346860d061d7731 +Author: Zach Sadecki <Zach.Sadecki@ripcode.com> +Date: Tue Jul 31 12:27:25 2007 -0500 + + tsec: fix multiple PHY support + + The change entitled "Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx" + broke multiple PHY support in tsec.c. This fixes it. + + Signed-off-by: Zach Sadecki <Zach.Sadecki@ripcode.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit dcb84b7208ade0bbebbeb56bec9c2c64f8b2eede +Author: Joe Hamman <joe.hamman@embeddedspecialties.com> +Date: Thu Aug 9 09:08:18 2007 -0500 + + tsec: Allow Ten Bit Interface address to be configurable + + Allow the address of the Ten Bit Interface (TBI) to be changed in the + event of a conflict with another device. + + Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com> + +commit 7c4c3722a38d40b0cf537ddae72b04f4088b190c +Author: Jason Jin <Jason.jin@freescale.com> +Date: Tue Aug 7 16:17:06 2007 +0800 + + Add CONFIG_BIOSEMU define to guard all the bios emulator code + + This patch fix the compile issue on the board that did not enable the bios emulator + +commit bf1060ea4f9eaa7e7d164a70a7d6f28939882053 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Aug 7 16:02:13 2007 +0200 + + Fix missing brace error in fs/fat/fat.c + [pointed out by Roderik Wildenburg] + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 6c33c78557ca6f8da68c01ce33e278695197d3f4 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Aug 6 23:21:05 2007 +0200 + + Fixed typo in README (pointed out by Martin Jost). + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 9c7e4b06214db61bb21f1bcbe57c97519669baae +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Aug 6 02:17:36 2007 +0200 + + Coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 221838cc7eb178370ff62aa05920a582e12ac322 +Author: Jason Jin <Jason.jin@freescale.com> +Date: Tue Jul 10 09:03:22 2007 +0800 + + Remove the bios emulator from MAI board. + + The bios emulator in the MAI board can not pass compile + and have a lot of crap in it. remove it and will have a + clean and small bios emulator in the drivers directory + which can be uesed for every board. + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit 5618332409bb96f4448d1712899369fc80c0b489 +Author: Jason Jin <Jason.jin@freescale.com> +Date: Fri Jul 13 12:14:59 2007 +0800 + + Fix some compile issues for MAI board. + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit 0f460a1ee148b648ee242c3157650287d4296260 +Author: Jason Jin <Jason.jin@freescale.com> +Date: Fri Jul 13 12:14:58 2007 +0800 + + Configurations for ATI video card BIOS emulator + + This patch add definition of the BIOS emulator and the ATI framebuffer + driver for MPC8641HPCN board. + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + Signed-off-by: Zhang Wei <wei.zhang@freescale.com> + +commit ece92f85053b8df613edcf05b26a416cbc3d629c +Author: Jason Jin <Jason.jin@freescale.com> +Date: Fri Jul 6 08:34:56 2007 +0800 + + This is a BIOS emulator, porting from SciTech for u-boot, mainly for + ATI video card BIOS. and can be used for x86 code emulation by some + modifications. + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit 5072188acabde3178fac7f5a597150e6e74fd40c +Author: Jason Jin <Jason.jin@freescale.com> +Date: Fri Jul 6 08:33:33 2007 +0800 + + This is a framebuffer driver for ATI video card, can work for PCI9200, + X300, X700, X800 ATI video cards. + + Signed-off-by: Zhang Wei <wei.zhang@freescale.com> + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + commit 5728be389e65fd47f34b33c2596271eb4db751ae Author: Wolfgang Denk <wd@denx.de> Date: Mon Aug 6 01:01:49 2007 +0200 @@ -42,6 +795,28 @@ Date: Thu Aug 2 14:09:49 2007 -0500 Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> +commit 86b116b1b1e165ca4840daefed36d2e3b8460173 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Fri Aug 3 12:08:16 2007 +0200 + + cm1_qp1 -> cm5200: single U-Boot image for modules from the cm5200 family. + + Add the ability for modules from the Schindler cm5200 family to use a + single U-Boot image: + - rename cm1_qp1 to cm5200 + - add run-time module detection + - parametrize SDRAM configuration according to the module we are running on + + Few minor, board-specific fixes included in this patch: + - better MAC address handling + - updated default environment ('update' command uses +{filesize} now) + - improved error messages in the auto-update code + - allow booting U-Boot from RAM (CFG_RAMBOOT) + + Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> + Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> + Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> + commit c7e717ebc2b044d7a71062552c9dc0f54ea9b779 Author: Andy Fleming <afleming@freescale.com> Date: Fri Aug 3 04:05:25 2007 -0500 @@ -2027,6 +2802,14 @@ Date: Wed May 23 18:47:48 2007 +0200 Signed-off-by: Detlev Zundel <dzu@denx.de> +commit 9b7464a2c88614e1061f509c48930a3d240d1a35 +Author: Jason Jin <Jason.jin@freescale.com> +Date: Mon Jun 11 15:14:24 2007 +0200 + + USB: This patch fix readl in ohci swap reg access. + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + commit 8f8416fada9faf94b9a92f21fe6000643cb521d5 Author: Bartlomiej Sieka <tur@semihalf.com> Date: Fri Jun 8 14:52:22 2007 +0200 @@ -2062,6 +2845,30 @@ Date: Wed Jun 6 16:26:56 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit 19d763c35e0b5568eaf0b8adbf7a68ccfe7fa243 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Wed Jun 6 11:49:44 2007 +0200 + + TRAB, USB: update trab board configuration for use of generic ohci driver + +commit dace45acd1c1357daa9322099d07c9a9e08b0024 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Wed Jun 6 11:49:43 2007 +0200 + + USB: ohci fixes and cleanup for ppc4xx and yosemite board. + +commit 72657570b61635c74fa0c3f0e9e7d0671a9d08df +Author: Markus Klotzbuecher <mk@denx.de> +Date: Wed Jun 6 11:49:43 2007 +0200 + + USB: ohci fixes and cleanup for mpc5xxx and IceCube board config + +commit fc43be478f2aa37ce38acd85355038866e4162af +Author: Markus Klotzbuecher <mk@denx.de> +Date: Wed Jun 6 11:49:35 2007 +0200 + + USB/OHCI: endianness cleanup in the generic ohci driver + commit c440bfe6d6d92d66478a7e84402b31f48413617b Author: Stefan Roese <sr@denx.de> Date: Wed Jun 6 11:42:13 2007 +0200 @@ -2082,6 +2889,73 @@ Date: Wed Jun 6 11:42:13 2007 +0200 Signed-off-by: Stefan Roese <sr@denx.de> +commit 18135125f909948b85d1d6881ab4ac0efb4a1c58 +Author: Rodolfo Giometti <giometti@linux.it> +Date: Wed Jun 6 10:08:14 2007 +0200 + + Files include/linux/byteorder/{big,little}_endian.h define + __BIG_ENDIAN and __LITTLE_ENDIAN. + + Signed-off-by: Rodolfo Giometti <giometti@linux.it> + +commit a81d1c0b85b13e9d45f2d87de96a51a6e0ef0f82 +Author: Zhang Wei <wei.zhang@freescale.com> +Date: Wed Jun 6 10:08:14 2007 +0200 + + Add USB PCI-OHCI, USB keyboard and event poll support to the + MPC8641HPCN board config file. + + Signed-off-by: Zhang Wei <wei.zhang@freescale.com> + +commit 4dae14ce8fbdf380017dc54f172218e7d2acc889 +Author: Zhang Wei <wei.zhang@freescale.com> +Date: Wed Jun 6 10:08:14 2007 +0200 + + USB PCI-OHCI, interrupt pipe and usb event poll support + + This patch added USB PCI-OHCI chips support, interrupt pipe support + and usb event poll support. For supporting the USB interrupt pipe, the + globe urb_priv is moved to purb in ed struct. Now, we can process + several urbs at one time. The interrupt pipe support codes are ported + from Linux kernel 2.4. + + Signed-off-by: Zhang Wei <wei.zhang@freescale.com> + +commit fdcfaa1b02268b2899e374b35adf936c911a47eb +Author: Zhang Wei <wei.zhang@freescale.com> +Date: Wed Jun 6 10:08:13 2007 +0200 + + USB event poll support + + This patch adds USB event poll support, which could be used in usbkbd + and other usb devices driver when the asynchronous interrupt + processing is supported. + + Signed-off-by: Zhang Wei <wei.zhang@freescale.com + +commit 9a1d00fa47c1e05e3fdb60b33213af4e18d4c18e +Author: Rodolfo Giometti <giometti@linux.it> +Date: Wed Jun 6 10:08:12 2007 +0200 + + ISP116x: delay for crappy USB keys + + Using some (very) slow USB keys cause the USB host controller buffers + are not ready to be read by the CPU so we need an extra delay before + reading the USB storage data. + + Signed-off-by: Rodolfo Giometti <giometti@linux.it> + +commit 09444143670c9c2243cb7aba9f70b3713d33bed1 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Wed Jun 6 10:08:12 2007 +0200 + + Change duplicate usb_cpu_init_fail to usb_board_init_fail + + Thanks to Liew Tsi Chung <Tsi-chung.Liew@freescale.com> for pointing + this out. + + Signed-off-by: Markus Klotzbuecher <mk@denx.de> + commit 32922cdc470fdfd39bea0c1c4f582d3fb340421e Author: Ed Swarthout <Ed.Swarthout@freescale.com> Date: Tue Jun 5 12:30:52 2007 -0500 @@ -2113,6 +2987,35 @@ Date: Mon Jun 4 08:36:05 2007 +0200 Signed-off-by: Benoit Monin <bmonin@adeneo.eu> Signed-off-by: Stefan Roese <sr@denx.de> +commit 5b1313fb2758ffce8b624457f777d8cc6709608d +Author: Nikita V. Youshchenko <yoush@debian.org> +Date: Wed May 23 12:45:19 2007 +0400 + + fix compilation problem for mpc8349itx CFG_RAMBOOT + + Current include/configs/MPC8349ITX.h does contain some support for building + image that will be started from memory (without putting in into flash). + It could be triggered by building with TEXT_BASE set to a low value. + + However, this support is incomplete: using of low TEXT_BASE causes + defining configuration macros in inconsistent way, which later leads + to compilation errors. In particular. flash support is being disabled, + but then flash structures get referenced. + + This patch fixes this, making it possible to build with low TEXT_BASE. + + Signed-Off-By: Nikita Youshchenko <yoush@debian.org> + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 8a364f0970de49949d635e60accf463c6443ef8c +Author: Nikita V. Youshchenko <yoush@debian.org> +Date: Wed May 23 12:45:25 2007 +0400 + + add missing 'console' var to default mpc8349itx config + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + commit 18d156eb37c90fadc8ec7a81a3b89176161f85b7 Author: Stefan Roese <sr@denx.de> Date: Fri Jun 1 16:18:17 2007 +0200 @@ -2800,6 +3703,12 @@ Date: Mon May 7 17:11:09 2007 +0200 new: add writing to msr register +commit 3a619dd7bed03e8b4d22a3911f90fd12af5376c2 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Mon May 7 16:43:56 2007 +0200 + + Fix an ancient CHANGELOG conflict + commit ac4cd59d59c9bf3f89cb7a344abf8184d678f562 Author: Timur Tabi <timur@freescale.com> Date: Sat May 5 08:12:30 2007 +0200 @@ -3496,6 +4405,17 @@ Date: Mon Apr 23 13:54:24 2007 +0200 Signed-off-by: Mike Frysinger <vapier@gentoo.org> +commit d98c0885ad617fccf21e7c26ef8cb728fbfb2459 +Author: Rodolfo Giometti <giometti@enneenne.com> +Date: Mon Apr 23 13:10:52 2007 +0200 + + USB: (Another) delay for crappy USB keys. + + Some USB keys are slow in giving back an answer when the Root HUB + enables power lines. + + Signed-off-by: Rodolfo Giometti <giometti@linux.it> + commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522 Author: Stefan Roese <sr@denx.de> Date: Mon Apr 23 12:00:22 2007 +0200 @@ -4161,6 +5081,22 @@ Date: Wed Apr 4 01:49:15 2007 +0200 Minor cleanup. +commit 822af351ad2babc7d99033361a5fcacd30f6bc78 +Author: Rodolfo Giometti <giometti@enneenne.com> +Date: Tue Apr 3 14:27:18 2007 +0200 + + Support for the Philips ISP116x HCD (Host Controller Driver) + + Signed-off-by: Rodolfo Giometti <giometti@enneenne.com> + +commit edf5851be6c17c031d4f71dd5b0a12040b7c50c8 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Tue Apr 3 14:27:08 2007 +0200 + + USB: cleanup monahans usb support. Remove dead code. + + Signed-off-by: Markus Klotzbuecher <mk@denx.de> + commit a65c5768e5537530bd1780af3d3fddc3113a163c Author: Stefan Roese <sr@denx.de> Date: Mon Apr 2 10:09:30 2007 +0200 @@ -4330,6 +5266,23 @@ Date: Tue Mar 27 00:32:16 2007 +0200 PATCH: Resolve GPL license problem +commit ae00bb4b2944dc64a485ed72a19754b11af7c223 +Author: Rodolfo Giometti <giometti@enneenne.com> +Date: Mon Mar 26 12:03:36 2007 +0200 + + PXA: pxa27x USB OHCI support + + Signed-off-by: Rodolfo Giometti <giometti@linux.it> + +commit ae79f60677c208326535647dcbd5c3ec40dbcb0b +Author: Markus Klotzbuecher <mk@denx.de> +Date: Mon Mar 26 11:21:05 2007 +0200 + + USB: remove the S3C24X0_merge #define, which was introduced while + merging OHCI drivers. + + Signed-off-by: Markus Klotzbuecher <mk@denx.de> + commit 1798049522f594013aea29457d46794298c6ae15 Author: Michal Simek <root@monstr.eu> Date: Mon Mar 26 01:39:07 2007 +0200 @@ -6455,6 +7408,34 @@ Date: Mon Nov 27 14:12:17 2006 +0100 Signed-off-by: Stefan Roese <sr@denx.de> +commit 58b485776698c3d71ec5a215e392123b4c15afa3 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Mon Nov 27 11:51:21 2006 +0100 + + Add a small README with information on the generic ohci driver. + +commit ae3b770e4eae8e98b6e9e29662e18c47fdf0171f +Author: Markus Klotzbuecher <mk@denx.de> +Date: Mon Nov 27 11:46:46 2006 +0100 + + Fix some endianness issues related to the generic ohci driver + +commit 7b59b3c7a8ce2e4b567abf99c1cd667bf35b9418 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Mon Nov 27 11:44:58 2006 +0100 + + Introduced the configuration option CONFIG_USB_OHCI_NEW in order to be able + to choose between the old and the generic OHCI drivers. + +commit 53e336e9ffc51035bdc4e5867631b3378761b4df +Author: Markus Klotzbuecher <mk@denx.de> +Date: Mon Nov 27 11:43:09 2006 +0100 + + Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driver + and adapted board configs TQM5200 and yosemite accordingly. This commit + also makes the maximum number of root hub ports configurable + (CFG_USB_OHCI_MAX_ROOT_PORTS). + commit 78d620ebb5871d252270dedfad60c6568993b780 Author: Wolfgang Denk <wd@atlas.denx.de> Date: Thu Nov 23 22:58:58 2006 +0100 @@ -8212,6 +9193,12 @@ Date: Tue Jun 27 18:11:54 2006 +0800 Signed-off-by: Jason Jin <Jason.jin@freescale.com> +commit 99d70e3a47affb9bae041a2caece7cd516e213b3 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Mon Jun 26 11:06:00 2006 +0200 + + More code cleanup + commit 684623ce92c5fd32e7db2d6e016945a67c5ffaba Author: Jon Loeliger <jdl@freescale.com> Date: Thu Jun 22 08:51:46 2006 -0500 @@ -8236,6 +9223,28 @@ Date: Thu Jun 15 21:33:37 2006 -0500 Signed-off-by: Jon Loeliger <jdl@freescale.com> +commit 386eda022473394ad8f36b86f2bdc9b4cb816291 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Wed Jun 14 18:14:56 2006 +0200 + + Code cleanup + +commit 16c8d5e76ae0f78f39a60608574adfe0feb9cc70 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Wed Jun 14 17:45:53 2006 +0200 + + Various USB related patches + - Add support for mpc8xx USB device. + - Add support for Common Device Class - Abstract Control Model USB console. + - Add support for flow control in USB slave devices. + - Add support for switching between gserial and cdc_acm using environment. + - Minor changes to usbdcore_omap1510.c usbdcore_omap1510.h + - Update usbcore slightly to ease host enumeration. + - Fix non-portable endian problems in usbdcore and usbdcore_ep0. + - Add AdderUSB_config as a defconfig to enable usage of the USB console + by default with the Adder87x U-Boot port. + Patches by Bryan O'Donoghue <bodonoghue@codehermit.ie>, 29 May 2006 + commit 8ecc971618f56029ad99d3516f8b297a6ed58971 Author: Jon Loeliger <jdl@jdl.com> Date: Wed Jun 7 10:53:55 2006 -0500 @@ -8314,6 +9323,12 @@ Date: Tue May 30 17:47:00 2006 -0500 Signed-off-by: Jon Loeliger <jdl@freescale.com> +commit ddf83a2fcef1a670c45fc585119dcc1fe062c4a9 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Tue May 30 16:56:14 2006 +0200 + + Support generic OHCI support for the s3c24x0 cpu. + commit 38cee12dcfcc257371c901c7e13e58ecab0a35d8 Author: Haiying Wang <Haiying.Wang@freescale.com> Date: Tue May 30 09:10:32 2006 -0500 @@ -8363,6 +9378,29 @@ Date: Fri May 26 10:01:16 2006 -0500 Signed-off-by: Jon Loeliger <jdl@jdl.com> +commit 301f1aa384d0edcae6a22fd9adb933ad71695ecc +Author: Markus Klotzbuecher <mk@denx.de> +Date: Tue May 23 13:38:35 2006 +0200 + + Changed the mp2usb (at91rm9200) board to use the generic OHCI driver. Some + fixes to the latter. + +commit 24e37645e7378b20fa8f20e2996c8fb8e90c70c9 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Tue May 23 10:33:11 2006 +0200 + + More cleanup for the delta board and the generic usb_ohci driver. Added + CFG_USB_BOARD_INIT and CFG_USB_CPU_INIT for enabling board and cpu specific + initialization and cleanup hooks respectively. + +commit 3e326ece9eba8184f5d48aa4fb87760a8f6f0f10 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Mon May 22 16:33:54 2006 +0200 + + This patch adds USB storage support for the delta board. This is the first + board to make use of a generic OHCI driver, that calls hooks for board + dependant initialization. + commit 14e37081ff3cac7ebe6e93836523429853b6b292 Author: Jon Loeliger <jdl@jdl.com> Date: Fri May 19 13:28:39 2006 -0500 @@ -252,6 +252,10 @@ E: Raghu.Krishnaprasad@fci.com D: Support for Adder-II MPC852T evaluation board W: http://www.forcecomputers.com +N: Sergey Kubushyn +E: ksi@koi8.net +D: Support for various TI DaVinci based boards. + N: Bernhard Kuhn E: bkuhn@metrowerks.com D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards diff --git a/MAINTAINERS b/MAINTAINERS index 703f2fe..5b17739 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -448,6 +448,12 @@ Nishant Kamat <nskamat@ti.com> omap1610h2 ARM926EJS +Sergey Kubushyn <ksi@koi8.net> + + DV-EVM ARM926EJS + SONATA ARM926EJS + SCHMOOGIE ARM926EJS + Prakash Kumar <prakash@embedx.com> cerf250 xscale @@ -26,124 +26,281 @@ LIST="" ## MPC5xx Systems ######################################################################### -LIST_5xx=" \ - cmi_mpc5xx \ +LIST_5xx=" \ + cmi_mpc5xx \ " ######################################################################### ## MPC5xxx Systems ######################################################################### -LIST_5xxx=" \ - BC3450 cm5200 cpci5200 EVAL5200 \ - fo300 icecube_5100 icecube_5200 lite5200b \ - mcc200 mecp5200 motionpro o2dnt \ - pf5200 PM520 TB5200 Total5100 \ - Total5200 Total5200_Rev2 TQM5200 TQM5200_B \ - TQM5200S v38b \ +LIST_5xxx=" \ + BC3450 \ + cm5200 \ + cpci5200 \ + EVAL5200 \ + fo300 \ + icecube_5100 \ + icecube_5200 \ + lite5200b \ + mcc200 \ + mecp5200 \ + motionpro \ + o2dnt \ + pf5200 \ + PM520 \ + TB5200 \ + Total5100 \ + Total5200 \ + Total5200_Rev2 \ + TQM5200 \ + TQM5200_B \ + TQM5200S \ + v38b \ " ######################################################################### ## MPC512x Systems ######################################################################### -LIST_512x=" \ - ads5121 \ +LIST_512x=" \ + ads5121 \ " ######################################################################### ## MPC8xx Systems ######################################################################### -LIST_8xx=" \ - Adder87x GENIETV MBX860T R360MPI \ - AdderII GTH MHPC RBC823 \ - ADS860 hermes MPC86xADS rmu \ - AMX860 IAD210 MPC885ADS RPXClassic \ - c2mon ICU862_100MHz MVS1 RPXlite \ - CCM IP860 NETPHONE RPXlite_DW \ - cogent_mpc8xx IVML24 NETTA RRvision \ - ELPT860 IVML24_128 NETTA2 SM850 \ - EP88x IVML24_256 NETTA_ISDN spc1920 \ - ESTEEM192E IVMS8 NETVIA SPD823TS \ - ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \ - FADS823 IVMS8_256 NX823 SXNI855T \ - FADS850SAR KUP4K pcu_e TOP860 \ - FADS860T KUP4X QS823 TQM823L \ - FLAGADM LANTEC QS850 TQM823L_LCD \ - FPS850L lwmon QS860T TQM850L \ - GEN860T MBX quantum TQM855L \ - GEN860T_SC TQM860L \ - TQM885D \ - uc100 \ - v37 \ +LIST_8xx=" \ + Adder87x \ + AdderII \ + ADS860 \ + AMX860 \ + c2mon \ + CCM \ + cogent_mpc8xx \ + ELPT860 \ + EP88x \ + ESTEEM192E \ + ETX094 \ + FADS823 \ + FADS850SAR \ + FADS860T \ + FLAGADM \ + FPS850L \ + GEN860T \ + GEN860T_SC \ + GENIETV \ + GTH \ + hermes \ + IAD210 \ + ICU862_100MHz \ + IP860 \ + IVML24 \ + IVML24_128 \ + IVML24_256 \ + IVMS8 \ + IVMS8_128 \ + IVMS8_256 \ + KUP4K \ + KUP4X \ + LANTEC \ + lwmon \ + MBX \ + MBX860T \ + MHPC \ + MPC86xADS \ + MPC885ADS \ + MVS1 \ + NETPHONE \ + NETTA \ + NETTA2 \ + NETTA_ISDN \ + NETVIA \ + NETVIA_V2 \ + NX823 \ + pcu_e \ + QS823 \ + QS850 \ + QS860T \ + quantum \ + R360MPI \ + RBC823 \ + rmu \ + RPXClassic \ + RPXlite \ + RPXlite_DW \ + RRvision \ + SM850 \ + spc1920 \ + SPD823TS \ + svm_sc8xx \ + SXNI855T \ + TOP860 \ + TQM823L \ + TQM823L_LCD \ + TQM850L \ + TQM855L \ + TQM860L \ + TQM885D \ + uc100 \ + v37 \ " ######################################################################### ## PPC4xx Systems ######################################################################### -LIST_4xx=" \ - acadia acadia_nand ADCIOP alpr \ - AP1000 AR405 ASH405 bamboo \ - bamboo_nand bubinga CANBT CMS700 \ - CPCI2DP CPCI405 CPCI4052 CPCI405AB \ - CPCI405DT CPCI440 CPCIISER4 CRAYL1 \ - csb272 csb472 DASA_SIM DP405 \ - DU405 ebony ERIC EXBITGEN \ - G2000 HH405 HUB405 JSE \ - KAREF katmai luan lwmon5 \ - METROBOX MIP405 MIP405T ML2 \ - ml300 ocotea OCRTC ORSG \ - p3p440 PCI405 pcs440ep PIP405 \ - PLU405 PMC405 PPChameleonEVB sbc405 \ - sc3 sequoia sequoia_nand taishan \ - VOH405 VOM405 W7OLMC W7OLMG \ - walnut WUH405 XPEDITE1K yellowstone \ - yosemite yucca \ +LIST_4xx=" \ + acadia \ + acadia_nand \ + ADCIOP \ + alpr \ + AP1000 \ + AR405 \ + ASH405 \ + bamboo \ + bamboo_nand \ + bubinga \ + CANBT \ + CMS700 \ + CPCI2DP \ + CPCI405 \ + CPCI4052 \ + CPCI405AB \ + CPCI405DT \ + CPCI440 \ + CPCIISER4 \ + CRAYL1 \ + csb272 \ + csb472 \ + DASA_SIM \ + DP405 \ + DU405 \ + ebony \ + ERIC \ + EXBITGEN \ + G2000 \ + HH405 \ + HUB405 \ + JSE \ + KAREF \ + katmai \ + luan \ + lwmon5 \ + METROBOX \ + MIP405 \ + MIP405T \ + ML2 \ + ml300 \ + ocotea \ + OCRTC \ + ORSG \ + p3p440 \ + PCI405 \ + pcs440ep \ + PIP405 \ + PLU405 \ + PMC405 \ + PPChameleonEVB \ + sbc405 \ + sc3 \ + sequoia \ + sequoia_nand \ + taishan \ + VOH405 \ + VOM405 \ + W7OLMC \ + W7OLMG \ + walnut \ + WUH405 \ + XPEDITE1K \ + yellowstone \ + yosemite \ + yucca \ " ######################################################################### ## MPC8220 Systems ######################################################################### -LIST_8220=" \ - Alaska8220 Yukon8220 \ +LIST_8220=" \ + Alaska8220 \ + Yukon8220 \ " ######################################################################### ## MPC824x Systems ######################################################################### -LIST_824x=" \ - A3000 barco BMW CPC45 \ - CU824 debris eXalion HIDDEN_DRAGON \ - MOUSSE MUSENKI MVBLUE \ - OXC PN62 Sandpoint8240 Sandpoint8245 \ - sbc8240 SL8245 utx8245 \ +LIST_824x=" \ + A3000 \ + barco \ + BMW \ + CPC45 \ + CU824 \ + debris \ + eXalion \ + HIDDEN_DRAGON \ + MOUSSE \ + MUSENKI \ + MVBLUE \ + OXC \ + PN62 \ + Sandpoint8240 \ + Sandpoint8245 \ + sbc8240 \ + SL8245 \ + utx8245 \ " ######################################################################### ## MPC8260 Systems (includes 8250, 8255 etc.) ######################################################################### -LIST_8260=" \ - atc cogent_mpc8260 CPU86 CPU87 \ - ep8248 ep8260 ep82xxm gw8260 \ - hymod IPHASE4539 ISPAN MPC8260ADS \ - MPC8266ADS MPC8272ADS PM826 PM828 \ - ppmc8260 Rattler8248 RPXsuper rsdproto \ - sacsng sbc8260 SCM TQM8260_AC \ - TQM8260_AD TQM8260_AE ZPC1900 \ +LIST_8260=" \ + atc \ + cogent_mpc8260 \ + CPU86 \ + CPU87 \ + ep8248 \ + ep8260 \ + ep82xxm \ + gw8260 \ + hymod \ + IPHASE4539 \ + ISPAN \ + MPC8260ADS \ + MPC8266ADS \ + MPC8272ADS \ + PM826 \ + PM828 \ + ppmc8260 \ + Rattler8248 \ + RPXsuper \ + rsdproto \ + sacsng \ + sbc8260 \ + SCM \ + TQM8260_AC \ + TQM8260_AD \ + TQM8260_AE \ + ZPC1900 \ " ######################################################################### ## MPC83xx Systems (includes 8349, etc.) ######################################################################### -LIST_83xx=" \ - MPC8313ERDB_33 MPC8313ERDB_66 MPC832XEMDS MPC8349EMDS \ - MPC8349ITX MPC8349ITXGP MPC8360EMDS sbc8349 \ - TQM834x \ +LIST_83xx=" \ + MPC8313ERDB_33 \ + MPC8313ERDB_66 \ + MPC832XEMDS \ + MPC8349EMDS \ + MPC8349ITX \ + MPC8349ITXGP \ + MPC8360EMDS \ + sbc8349 \ + TQM834x \ " @@ -151,20 +308,33 @@ LIST_83xx=" \ ## MPC85xx Systems (includes 8540, 8560 etc.) ######################################################################### -LIST_85xx=" \ - MPC8540ADS MPC8540EVAL MPC8541CDS MPC8544DS \ - MPC8548CDS MPC8555CDS MPC8560ADS MPC8568MDS \ - PM854 PM856 sbc8540 sbc8560 \ - stxgp3 stxssa TQM8540 TQM8541 \ - TQM8555 TQM8560 \ +LIST_85xx=" \ + MPC8540ADS \ + MPC8540EVAL \ + MPC8541CDS \ + MPC8544DS \ + MPC8548CDS \ + MPC8555CDS \ + MPC8560ADS \ + MPC8568MDS \ + PM854 \ + PM856 \ + sbc8540 \ + sbc8560 \ + stxgp3 \ + stxssa \ + TQM8540 \ + TQM8541 \ + TQM8555 \ + TQM8560 \ " ######################################################################### ## MPC86xx Systems ######################################################################### -LIST_86xx=" \ - MPC8641HPCN \ +LIST_86xx=" \ + MPC8641HPCN \ SBC8641D \ " @@ -172,103 +342,193 @@ LIST_86xx=" \ ## 74xx/7xx Systems ######################################################################### -LIST_74xx=" \ - DB64360 DB64460 EVB64260 P3G4 \ - p3m7448 PCIPPC2 PCIPPC6 ZUMA \ - mpc7448hpc2 +LIST_74xx=" \ + DB64360 \ + DB64460 \ + EVB64260 \ + mpc7448hpc2 \ + P3G4 \ + p3m7448 \ + PCIPPC2 \ + PCIPPC6 \ + ZUMA \ " -LIST_7xx=" \ - BAB7xx CPCI750 ELPPC p3m750 \ - ppmc7xx \ +LIST_7xx=" \ + BAB7xx \ + CPCI750 \ + ELPPC \ + p3m750 \ + ppmc7xx \ " -LIST_ppc="${LIST_5xx} ${LIST_5xxx} \ - ${LIST_8xx} \ - ${LIST_8220} ${LIST_824x} ${LIST_8260} \ - ${LIST_83xx} \ - ${LIST_85xx} \ - ${LIST_86xx} \ - ${LIST_4xx} \ - ${LIST_74xx} ${LIST_7xx}" +LIST_ppc=" \ + ${LIST_5xx} \ + ${LIST_5xxx} \ + ${LIST_8xx} \ + ${LIST_8220} \ + ${LIST_824x} \ + ${LIST_8260} \ + ${LIST_83xx} \ + ${LIST_85xx} \ + ${LIST_86xx} \ + ${LIST_4xx} \ + ${LIST_74xx} \ + ${LIST_7xx} \ +" ######################################################################### ## StrongARM Systems ######################################################################### -LIST_SA="assabet dnp1110 gcplus lart shannon" +LIST_SA=" \ + assabet \ + dnp1110 \ + gcplus \ + lart \ + shannon \ +" ######################################################################### ## ARM7 Systems ######################################################################### -LIST_ARM7=" \ - armadillo B2 ep7312 evb4510 \ - impa7 integratorap ap7 ap720t \ - lpc2292sodimm modnet50 SMN42 \ +LIST_ARM7=" \ + ap7 \ + ap720t \ + armadillo \ + B2 \ + ep7312 \ + evb4510 \ + impa7 \ + integratorap \ + lpc2292sodimm \ + modnet50 \ + SMN42 \ " ######################################################################### ## ARM9 Systems ######################################################################### -LIST_ARM9=" \ - at91rm9200dk cmc_pu2 \ - ap920t ap922_XA10 ap926ejs ap946es \ - ap966 cp920t cp922_XA10 cp926ejs \ - cp946es cp966 lpd7a400 mp2usb \ - mx1ads mx1fs2 netstar omap1510inn \ - omap1610h2 omap1610inn omap730p2 sbc2410x \ - scb9328 smdk2400 smdk2410 trab \ - VCMA9 versatile versatileab versatilepb \ - voiceblue \ +LIST_ARM9=" \ + at91rm9200dk \ + cmc_pu2 \ + ap920t \ + ap922_XA10 \ + ap926ejs \ + ap946es \ + ap966 \ + cp920t \ + cp922_XA10 \ + cp926ejs \ + cp946es \ + cp966 \ + lpd7a400 \ + mp2usb \ + mx1ads \ + mx1fs2 \ + netstar \ + omap1510inn \ + omap1610h2 \ + omap1610inn \ + omap730p2 \ + sbc2410x \ + scb9328 \ + smdk2400 \ + smdk2410 \ + trab \ + VCMA9 \ + versatile \ + versatileab \ + versatilepb \ + voiceblue \ + davinci_dvevm \ + davinci_schmoogie \ + davinci_sonata \ " ######################################################################### ## ARM10 Systems ######################################################################### -LIST_ARM10=" \ - integratorcp cp1026 \ +LIST_ARM10=" \ + integratorcp \ + cp1026 \ " ######################################################################### ## ARM11 Systems ######################################################################### -LIST_ARM11=" \ - cp1136 omap2420h4 \ +LIST_ARM11=" \ + cp1136 \ + omap2420h4 \ " ######################################################################### ## Xscale Systems ######################################################################### -LIST_pxa=" \ - adsvix cerf250 cradle csb226 \ - delta innokom lubbock pleb2 \ - pxa255_idp wepep250 xaeniax xm250 \ - xsengine zylonite \ +LIST_pxa=" \ + adsvix \ + cerf250 \ + cradle \ + csb226 \ + delta \ + innokom \ + lubbock \ + pleb2 \ + pxa255_idp \ + wepep250 \ + xaeniax \ + xm250 \ + xsengine \ + zylonite \ " -LIST_ixp="ixdp425 ixdpg425 pdnb3 scpu" +LIST_ixp=" \ + ixdp425 \ + ixdpg425 \ + pdnb3 \ + scpu \ +" -LIST_arm=" \ - ${LIST_SA} \ - ${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11} \ - ${LIST_pxa} ${LIST_ixp} \ +LIST_arm=" \ + ${LIST_SA} \ + ${LIST_ARM7} \ + ${LIST_ARM9} \ + ${LIST_ARM10} \ + ${LIST_ARM11} \ + ${LIST_pxa} \ + ${LIST_ixp} \ " ######################################################################### ## MIPS Systems (default = big endian) ######################################################################### -LIST_mips4kc="incaip" +LIST_mips4kc=" \ + incaip \ +" -LIST_mips5kc="purple" +LIST_mips5kc=" \ + purple \ +" -LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2" +LIST_au1xx0=" \ + dbau1000 \ + dbau1100 \ + dbau1500 \ + dbau1550 \ + dbau1550_el \ + gth2 \ +" -LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}" +LIST_mips=" \ + ${LIST_mips4kc} \ + ${LIST_mips5kc} \ + ${LIST_au1xx0} \ +" ######################################################################### ## MIPS Systems (little endian) @@ -278,36 +538,55 @@ LIST_mips4kc_el="" LIST_mips5kc_el="" -LIST_au1xx0_el="dbau1550_el" +LIST_au1xx0_el=" \ + dbau1550_el \ +" -LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}" +LIST_mips_el=" \ + ${LIST_mips4kc_el} \ + ${LIST_mips5kc_el} \ + ${LIST_au1xx0_el} \ +" ######################################################################### ## i386 Systems ######################################################################### -LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel" +LIST_I486=" \ + sc520_cdp \ + sc520_spunk \ + sc520_spunk_rel \ +" -LIST_x86="${LIST_I486}" +LIST_x86=" \ + ${LIST_I486} \ +" ######################################################################### ## NIOS Systems ######################################################################### -LIST_nios=" \ - ADNPESC1 ADNPESC1_base_32 \ - ADNPESC1_DNPEVA2_base_32 \ - DK1C20 DK1C20_standard_32 \ - DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ +LIST_nios=" \ + ADNPESC1 \ + ADNPESC1_base_32 \ + ADNPESC1_DNPEVA2_base_32\ + DK1C20 \ + DK1C20_standard_32 \ + DK1S10 \ + DK1S10_standard_32 \ + DK1S10_mtx_ldk_20 \ " ######################################################################### ## Nios-II Systems ######################################################################### -LIST_nios2=" \ - EP1C20 EP1S10 EP1S40 \ - PCI5441 PK1C20 \ +LIST_nios2=" \ + EP1C20 \ + EP1S10 \ + EP1S40 \ + PCI5441 \ + PK1C20 \ " ######################################################################### @@ -315,31 +594,44 @@ LIST_nios2=" \ ######################################################################### LIST_microblaze=" \ - suzaku ml401 xupv2p + suzaku \ + ml401 \ + xupv2p \ " ######################################################################### ## ColdFire Systems ######################################################################### -LIST_coldfire=" \ - cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \ - idmr M5271EVB M5272C3 M5282EVB \ - TASREG r5200 M5271EVB \ +LIST_coldfire=" \ + cobra5272 \ + EB+MCF-EV123 \ + EB+MCF-EV123_internal \ + idmr \ + M5271EVB \ + M5272C3 \ + M5282EVB \ + TASREG \ + r5200 \ " ######################################################################### ## AVR32 Systems ######################################################################### -LIST_avr32="atstk1002" +LIST_avr32=" \ + atstk1002 \ +" ######################################################################### ## Blackfin Systems ######################################################################### -LIST_blackfin=" \ - bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit \ +LIST_blackfin=" \ + bf533-ezkit \ + bf533-stamp \ + bf537-stamp \ + bf561-ezkit \ " #----------------------------------------------------------------------- @@ -2023,6 +2023,15 @@ omap1510inn_config : unconfig omap5912osk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap +davinci_dvevm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci + +davinci_schmoogie_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci + +davinci_sonata_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci + omap1610inn_config \ omap1610inn_cs0boot_config \ omap1610inn_cs3boot_config \ @@ -228,114 +228,9 @@ build a config tool - later. The following options need to be configured: -- CPU Type: Define exactly one of - - PowerPC based CPUs: - ------------------- - CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860 - or CONFIG_MPC5xx - or CONFIG_MPC8220 - or CONFIG_MPC824X, CONFIG_MPC8260 - or CONFIG_MPC85xx - or CONFIG_IOP480 - or CONFIG_405GP - or CONFIG_405EP - or CONFIG_440 - or CONFIG_MPC74xx - or CONFIG_750FX - - ARM based CPUs: - --------------- - CONFIG_SA1110 - CONFIG_ARM7 - CONFIG_PXA250 - CONFIG_PXA27X - CONFIG_CPU_MONAHANS - - MicroBlaze based CPUs: - ---------------------- - CONFIG_MICROBLAZE - - Nios-2 based CPUs: - ---------------------- - CONFIG_NIOS2 - - AVR32 based CPUs: - ---------------------- - CONFIG_AT32AP - -- Board Type: Define exactly one of - - PowerPC based boards: - --------------------- - - CONFIG_ADCIOP CONFIG_FPS860L CONFIG_OXC - CONFIG_ADS860 CONFIG_GEN860T CONFIG_PCI405 - CONFIG_AMX860 CONFIG_GENIETV CONFIG_PCIPPC2 - CONFIG_AP1000 CONFIG_GTH CONFIG_PCIPPC6 - CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e - CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405 - CONFIG_BC3450 CONFIG_hymod CONFIG_PM826 - CONFIG_c2mon CONFIG_IAD210 CONFIG_ppmc8260 - CONFIG_CANBT CONFIG_ICU862 CONFIG_QS823 - CONFIG_CCM CONFIG_IP860 CONFIG_QS850 - CONFIG_CMI CONFIG_IPHASE4539 CONFIG_QS860T - CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RBC823 - CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXClassic - CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXlite - CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_RPXsuper - CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_rsdproto - CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_sacsng - CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8240 - CONFIG_CSB272 CONFIG_LANTEC CONFIG_Sandpoint8245 - CONFIG_CU824 CONFIG_LITE5200B CONFIG_sbc8260 - CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8560 - CONFIG_DB64360 CONFIG_MBX CONFIG_SM850 - CONFIG_DB64460 CONFIG_MBX860T CONFIG_SPD823TS - CONFIG_DU405 CONFIG_MHPC CONFIG_STXGP3 - CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_SXNI855T - CONFIG_EBONY CONFIG_MOUSSE CONFIG_TQM823L - CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM8260 - CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM850L - CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM855L - CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM860L - CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TTTech - CONFIG_ETX094 CONFIG_MVS1 CONFIG_UTX8245 - CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_V37 - CONFIG_FADS823 CONFIG_NETTA CONFIG_W7OLMC - CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMG - CONFIG_FADS860T CONFIG_NX823 CONFIG_WALNUT - CONFIG_FLAGADM CONFIG_OCRTC CONFIG_ZPC1900 - CONFIG_FPS850L CONFIG_ORSG CONFIG_ZUMA - - ARM based boards: - ----------------- - - CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250, - CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110, - CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, - CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, - CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400, - CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, - CONFIG_PLEB2, CONFIG_SHANNON, CONFIG_P2_OMAP730, - CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB, - CONFIG_VCMA9 - - MicroBlaze based boards: - ------------------------ - - CONFIG_SUZAKU - - Nios-2 based boards: - ------------------------ - - CONFIG_PCI5441 CONFIG_PK1C20 - CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40 - - AVR32 based boards: - ------------------- - - CONFIG_ATSTK1000 +- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX. + +- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS. - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) Define exactly one of @@ -2492,34 +2387,7 @@ is done by typing: make NAME_config where "NAME_config" is the name of one of the existing -configurations; the following names are supported: - - ADCIOP_config FPS860L_config omap730p2_config - ADS860_config GEN860T_config pcu_e_config - Alaska8220_config - AR405_config GENIETV_config PIP405_config - at91rm9200dk_config GTH_config QS823_config - CANBT_config hermes_config QS850_config - cmi_mpc5xx_config hymod_config QS860T_config - cogent_common_config IP860_config RPXlite_config - cogent_mpc8260_config IVML24_config RPXlite_DW_config - cogent_mpc8xx_config IVMS8_config RPXsuper_config - CPCI405_config JSE_config rsdproto_config - CPCIISER4_config LANTEC_config Sandpoint8240_config - csb272_config lwmon_config sbc8260_config - CU824_config MBX860T_config sbc8560_33_config - DUET_ADS_config MBX_config sbc8560_66_config - EBONY_config mpc7448hpc2_config SM850_config - ELPT860_config MPC8260ADS_config SPD823TS_config - ESTEEM192E_config MPC8540ADS_config stxgp3_config - ETX094_config MPC8540EVAL_config SXNI855T_config - FADS823_config NMPC8560ADS_config TQM823L_config - FADS850SAR_config NETVIA_config TQM850L_config - FADS860T_config omap1510inn_config TQM855L_config - FPS850L_config omap1610h2_config TQM860L_config - omap1610inn_config walnut_config - omap5912osk_config Yukon8220_config - omap2420h4_config ZPC1900_config +configurations; see the main Makefile for supported names. Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index c8bfdb8..f275ce7 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -85,9 +85,7 @@ long int initdram (int board_type) { u32 msize = 0; - puts ("Initializing\n"); msize = fixed_sdram (); - puts (" DDR RAM: "); return msize; } diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 5119a99..fd9b914 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -27,7 +27,7 @@ #include <i2c.h> #include <usb.h> -#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#ifdef CONFIG_CMD_BSB int do_i2c(char *argv[]) { @@ -445,4 +445,4 @@ U_BOOT_CMD( "fkt usb\n" " - Test USB communication\n" ); -#endif /* CFG_CMD_BSP */ +#endif /* CONFIG_CMD_BSP */ diff --git a/board/davinci/dv-evm/Makefile b/board/davinci/dv-evm/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/davinci/dv-evm/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dv-evm/board_init.S b/board/davinci/dv-evm/board_init.S new file mode 100644 index 0000000..22d8adc --- /dev/null +++ b/board/davinci/dv-evm/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/dv-evm/config.mk b/board/davinci/dv-evm/config.mk new file mode 100644 index 0000000..aa89d0e --- /dev/null +++ b/board/davinci/dv-evm/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> +# +# (C) Copyright 2003 +# Texas Instruments, <www.ti.com> +# Swaminathan <swami.iyer@ti.com> +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c new file mode 100644 index 0000000..94925ec --- /dev/null +++ b/board/davinci/dv-evm/dv_board.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> + +#define MACH_TYPE_DAVINCI_EVM 901 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1); + + setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc")); + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/dv-evm/u-boot.lds b/board/davinci/dv-evm/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/davinci/dv-evm/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/davinci/schmoogie/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S new file mode 100644 index 0000000..22d8adc --- /dev/null +++ b/board/davinci/schmoogie/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk new file mode 100644 index 0000000..aa89d0e --- /dev/null +++ b/board/davinci/schmoogie/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> +# +# (C) Copyright 2003 +# Texas Instruments, <www.ti.com> +# Swaminathan <swami.iyer@ti.com> +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c new file mode 100644 index 0000000..b15c5f7 --- /dev/null +++ b/board/davinci/schmoogie/dv_board.c @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> + +#define MACH_TYPE_SCHMOOGIE 1255 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + /* Set serial number from UID chip */ + u_int8_t crc_tbl[256] = { + 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, + 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, + 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, + 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, + 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, + 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62, + 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d, + 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, + 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, + 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07, + 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58, + 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, + 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6, + 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, + 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, + 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9, + 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f, + 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, + 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, + 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50, + 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, + 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee, + 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1, + 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, + 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, + 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, + 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, + 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, + 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a, + 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, + 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, + 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 + }; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set serial number from UID chip */ + if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) { + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + if (buf[0] != 0x70) { /* Device Family Code */ + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } + } + /* Now check CRC */ + tmp[0] = 0; + for (i = 0; i < 8; i++) + tmp[0] = crc_tbl[tmp[0] ^ buf[i]]; + + if (tmp[0] != 0) { + printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + /* CRC OK, set "serial" env variable */ + sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", + buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); + forceenv("serial#", (char *)&tmp[0]); + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/schmoogie/u-boot.lds b/board/davinci/schmoogie/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/davinci/schmoogie/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/davinci/sonata/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S new file mode 100644 index 0000000..fbb9ea7 --- /dev/null +++ b/board/davinci/sonata/board_init.S @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer + * Sonata boards, AFAIK, don't use this so it's just return by default. Ask + * Visioneering if they reinvented the wheel once again to make sure :) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.globl dv_board_init +dv_board_init: +#ifdef SONATA_BOARD_GPIOWP + /* Set PINMUX0 to enable GPIO4 */ + ldr r0, _PINMUX0 + ldr r1, GPIO4_EN_MASK + ldr r2, [r0] + and r2, r2, r1 + str r2, [r0] + + /* Enable GPIO LPSC module */ + ldr r0, PTSTAT + +gpio_ptstat_loop1: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop1 + + ldr r1, MDCTL_GPIO + ldr r2, [r1] + and r2, r2, $0xfffffff8 + orr r2, r2, $0x00000003 + str r2, [r1] + + orr r2, r2, $0x00000200 + str r2, [r1] + + ldr r1, PTCMD + mov r2, $0x00000001 + str r2, [r1] + +gpio_ptstat_loop2: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop2 + + ldr r0, MDSTAT_GPIO +gpio_mdstat_loop: + ldr r2, [r0] + and r2, r2, $0x0000001f + teq r2, $0x00000003 + bne gpio_mdstat_loop + + /* GPIO4 -> output */ + ldr r0, GPIO_DIR01 + mov r1, $0x10 + ldr r2, [r0] + bic r2, r2, r0 + str r2, [r0] + + /* Set it to 0 (Write Protect) */ + ldr r0, GPIO_CLR_DATA01 + str r1, [r0] +#endif + + mov pc, lr + +#ifdef SONATA_BOARD_GPIOWP +.ltorg + +GPIO4_EN_MASK: + .word 0xf77fffff +MDCTL_GPIO: + .word 0x01c41a68 +MDSTAT_GPIO: + .word 0x01c41868 +GPIO_DIR01: + .word 0x01c67010 +GPIO_CLR_DATA01: + .word 0x01c6701c +#endif diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk new file mode 100644 index 0000000..aa89d0e --- /dev/null +++ b/board/davinci/sonata/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> +# +# (C) Copyright 2003 +# Texas Instruments, <www.ti.com> +# Swaminathan <swami.iyer@ti.com> +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c new file mode 100644 index 0000000..7b0a459 --- /dev/null +++ b/board/davinci/sonata/dv_board.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> + +#define MACH_TYPE_SONATA 1254 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SONATA; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/sonata/u-boot.lds b/board/davinci/sonata/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/davinci/sonata/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 6044565..28e4c87 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -330,6 +330,8 @@ int do_auto_update(void) int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; char *env; long start, end; + +#if 0 /* disable key-press detection to speed up boot-up time */ uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0}; /* @@ -347,6 +349,7 @@ int do_auto_update(void) return 0; } +#endif au_usb_stor_curr_dev = -1; /* start USB */ if (usb_stop() < 0) { @@ -364,18 +367,21 @@ int do_auto_update(void) au_usb_stor_curr_dev = usb_stor_scan(0); if (au_usb_stor_curr_dev == -1) { debug ("No device found. Not initialized?\n"); - return -1; + res = -1; + goto xit; } /* check whether it has a partition table */ stor_dev = get_dev("usb", 0); if (stor_dev == NULL) { debug ("uknown device type\n"); - return -1; + res = -1; + goto xit; } if (fat_register_device(stor_dev, 1) != 0) { debug ("Unable to use USB %d:%d for fatls\n", au_usb_stor_curr_dev, 1); - return -1; + res = -1; + goto xit; } if (file_fat_detectfs() != 0) { debug ("file_fat_detectfs failed\n"); @@ -504,7 +510,7 @@ int do_auto_update(void) } while (res < 0); #endif } - usb_stop(); + /* restore the old state */ disable_ctrlc(old_ctrlc); #ifdef CONFIG_PROGRESSBAR @@ -517,6 +523,8 @@ int do_auto_update(void) lcd_enable(); } #endif - return 0; + xit: + usb_stop(); + return res; } #endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 696423e..e247fee 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -879,7 +879,7 @@ int ide_preinit (void) } #endif -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) void ide_set_reset (int idereset) { debug ("ide_reset(%d)\n", idereset); @@ -890,4 +890,4 @@ void ide_set_reset (int idereset) } udelay (10000); } -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 92120b0..54d3645 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -450,7 +450,7 @@ do_auto_update(void) { block_dev_desc_t *stor_dev; long sz; - int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc; + int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; char *env; long start, end; @@ -477,18 +477,21 @@ do_auto_update(void) au_usb_stor_curr_dev = usb_stor_scan(0); if (au_usb_stor_curr_dev == -1) { debug ("No device found. Not initialized?\n"); - return -1; + res = -1; + goto xit; } /* check whether it has a partition table */ stor_dev = get_dev("usb", 0); if (stor_dev == NULL) { debug ("uknown device type\n"); - return -1; + res = -1; + goto xit; } if (fat_register_device(stor_dev, 1) != 0) { debug ("Unable to use USB %d:%d for fatls\n", au_usb_stor_curr_dev, 1); - return -1; + res = -1; + goto xit; } if (file_fat_detectfs() != 0) { debug ("file_fat_detectfs failed\n"); @@ -648,9 +651,10 @@ do_auto_update(void) /* enable the power switch */ *CPLD_VFD_BK &= ~POWER_OFF; } - usb_stop(); /* restore the old state */ disable_ctrlc(old_ctrlc); - return 0; +xit: + usb_stop(); + return res; } #endif /* CONFIG_AUTO_UPDATE */ diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 2436581..e19f83e 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -45,8 +45,8 @@ DECLARE_GLOBAL_DATA_PTR; - /*cmd_boot.c*/ - extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +/*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) #include <rtc.h> @@ -362,7 +362,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (i != BZ_OK) { printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i); show_boot_progress (-6); - udelay(100000); do_reset (cmdtp, flag, argc, argv); } break; @@ -741,59 +740,65 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if(argc > 3) { of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); hdr = (image_header_t *)of_flat_tree; -#if defined(CONFIG_OF_LIBFDT) - if (fdt_check_header(of_flat_tree) == 0) { +#if defined(CONFIG_OF_FLAT_TREE) + if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { #else - if (*(ulong *)of_flat_tree == OF_DT_HEADER) { + if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) { #endif #ifndef CFG_NO_FLASH if (addr2info((ulong)of_flat_tree) != NULL) of_data = (ulong)of_flat_tree; #endif } else if (ntohl(hdr->ih_magic) == IH_MAGIC) { - printf("## Flat Device Tree Image at %08lX\n", hdr); + printf("## Flat Device Tree at %08lX\n", hdr); print_image_hdr(hdr); if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) && ((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) { - printf ("ERROR: Load address overwrites Flat Device Tree uImage\n"); - return; + puts ("ERROR: fdt overwritten - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } - printf(" Verifying Checksum ... "); + puts (" Verifying Checksum ... "); memmove (&header, (char *)hdr, sizeof(image_header_t)); checksum = ntohl(header.ih_hcrc); header.ih_hcrc = 0; if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) { - printf("ERROR: Flat Device Tree header checksum is invalid\n"); - return; + puts ("ERROR: fdt header checksum invalid - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } checksum = ntohl(hdr->ih_dcrc); addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t)); if(checksum != crc32(0, (uchar *)addr, ntohl(hdr->ih_size))) { - printf("ERROR: Flat Device Tree checksum is invalid\n"); - return; + puts ("ERROR: fdt checksum invalid - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } - printf("OK\n"); + puts ("OK\n"); if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) { - printf ("ERROR: uImage not Flat Device Tree type\n"); - return; + puts ("ERROR: uImage is not a fdt - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } if (ntohl(hdr->ih_comp) != IH_COMP_NONE) { - printf("ERROR: uImage is not uncompressed\n"); - return; + puts ("ERROR: uImage is compressed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } -#if defined(CONFIG_OF_LIBFDT) - if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) == 0) { -#else +#if defined(CONFIG_OF_FLAT_TREE) if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { +#else + if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) { #endif - printf ("ERROR: uImage data is not a flat device tree\n"); - return; + puts ("ERROR: uImage data is not a fdt - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } memmove((void *)ntohl(hdr->ih_load), @@ -801,10 +806,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, ntohl(hdr->ih_size)); of_flat_tree = (char *)ntohl(hdr->ih_load); } else { - printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree); - return; + puts ("Did not find a flat Flat Device Tree.\n" + "Must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } - printf (" Booting using flat device tree at 0x%x\n", + printf (" Booting using the fdt at 0x%x\n", of_flat_tree); } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1]) && (len_ptr[2])) { u_long tail = ntohl(len_ptr[0]) % 4; @@ -828,22 +834,24 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, of_data += 4 - tail; } -#if defined(CONFIG_OF_LIBFDT) - if (fdt_check_header((void *)of_data) != 0) { +#if defined(CONFIG_OF_FLAT_TREE) + if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { #else - if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) { + if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) { #endif - printf ("ERROR: image is not a flat device tree\n"); - return; + puts ("ERROR: image is not a fdt - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } -#if defined(CONFIG_OF_LIBFDT) - if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) { -#else +#if defined(CONFIG_OF_FLAT_TREE) if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) { +#else + if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) { #endif - printf ("ERROR: flat device tree size does not agree with image\n"); - return; + puts ("ERROR: fdt size != image size - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } } #endif @@ -916,15 +924,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_end = 0; } - debug ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong)kernel); - - show_boot_progress (15); - -#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) - unlock_ram_in_cache(); -#endif - #if defined(CONFIG_OF_LIBFDT) /* move of_flat_tree if needed */ if (of_data) { @@ -944,32 +943,41 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, of_flat_tree = (char *)of_start; printf (" Loading Device Tree to %08lx, end %08lx ... ", of_start, of_start + of_len - 1); - err = fdt_open_into((void *)of_start, (void *)of_data, of_len); + err = fdt_open_into((void *)of_data, (void *)of_start, of_len); if (err != 0) { - printf ("libfdt: %s " __FILE__ " %d\n", fdt_strerror(err), __LINE__); - } - /* - * Add the chosen node if it doesn't exist, add the env and bd_t - * if the user wants it (the logic is in the subroutines). - */ - if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { - printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree); - return; + puts ("ERROR: fdt move failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } + } + /* + * Add the chosen node if it doesn't exist, add the env and bd_t + * if the user wants it (the logic is in the subroutines). + */ + if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { + puts ("ERROR: /chosen node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #ifdef CONFIG_OF_HAS_UBOOT_ENV - if (fdt_env(of_flat_tree) < 0) { - printf("Failed creating the /u-boot-env node, aborting.\n"); - return; - } + if (fdt_env(of_flat_tree) < 0) { + puts ("ERROR: /u-boot-env node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #endif #ifdef CONFIG_OF_HAS_BD_T - if (fdt_bd_t(of_flat_tree) < 0) { - printf("Failed creating the /bd_t node, aborting.\n"); - return; - } -#endif + if (fdt_bd_t(of_flat_tree) < 0) { + puts ("ERROR: /bd_t node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); } #endif +#ifdef CONFIG_OF_BOARD_SETUP + /* Call the board-specific fixup routine */ + ft_board_setup(of_flat_tree, gd->bd); +#endif +#endif /* CONFIG_OF_LIBFDT */ #if defined(CONFIG_OF_FLAT_TREE) /* move of_flat_tree if needed */ if (of_data) { @@ -989,8 +997,36 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, of_start, of_start + of_len - 1); memmove ((void *)of_start, (void *)of_data, of_len); } + /* + * Create the /chosen node and modify the blob with board specific + * values as needed. + */ + ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); + /* ft_dump_blob(of_flat_tree); */ +#endif + debug ("## Transferring control to Linux (at address %08lx) ...\n", + (ulong)kernel); + + show_boot_progress (15); + +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) + unlock_ram_in_cache(); #endif +#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT) + if (of_flat_tree) { /* device tree; boot new style */ + /* + * Linux Kernel Parameters (passing device tree): + * r3: pointer to the fdt, followed by the board info data + * r4: physical pointer to the kernel itself + * r5: NULL + * r6: NULL + * r7: NULL + */ + (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); + /* does not return */ + } +#endif /* * Linux Kernel Parameters (passing board info data): * r3: ptr to board info data @@ -999,46 +1035,8 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, * r6: Start of command line string * r7: End of command line string */ -#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT) - if (!of_flat_tree) /* no device tree; boot old style */ -#endif - (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); - /* does not return */ - -#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT) - /* - * Linux Kernel Parameters (passing device tree): - * r3: ptr to OF flat tree, followed by the board info data - * r4: physical pointer to the kernel itself - * r5: NULL - * r6: NULL - * r7: NULL - */ -#if defined(CONFIG_OF_FLAT_TREE) - ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); - /* ft_dump_blob(of_flat_tree); */ -#endif -#if defined(CONFIG_OF_LIBFDT) - if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { - printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree); - return; - } -#ifdef CONFIG_OF_HAS_UBOOT_ENV - if (fdt_env(of_flat_tree) < 0) { - printf("Failed creating the /u-boot-env node, aborting.\n"); - return; - } -#endif -#ifdef CONFIG_OF_HAS_BD_T - if (fdt_bd_t(of_flat_tree) < 0) { - printf("Failed creating the /bd_t node, aborting.\n"); - return; - } -#endif -#endif /* if defined(CONFIG_OF_LIBFDT) */ - - (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); -#endif + (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + /* does not return */ } #endif /* CONFIG_PPC */ diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 08fe351..571b8f1 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -37,46 +37,32 @@ #include <fdt_support.h> #define MAX_LEVEL 32 /* how deeply nested we will go */ -#define SCRATCHPAD 1024 /* bytes of scratchpad memory */ +#define SCRATCHPAD 1024 /* bytes of scratchpad memory */ /* * Global data (for the gd->bd) */ DECLARE_GLOBAL_DATA_PTR; -/* - * Scratchpad memory. - */ -static char data[SCRATCHPAD]; - - -/* - * Function prototypes/declarations. - */ static int fdt_valid(void); -static void print_data(const void *data, int len); - +static int fdt_parse_prop(char *pathp, char *prop, char *newval, + char *data, int *len); +static int fdt_print(char *pathp, char *prop, int depth); /* * Flattened Device Tree command, see the help for parameter definitions. */ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - char op; - if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } - /* - * Figure out which subcommand was given - */ - op = argv[1][0]; /******************************************************************** * Set the address of the fdt ********************************************************************/ - if (op == 'a') { + if (argv[1][0] == 'a') { /* * Set the address [and length] of the fdt. */ @@ -94,7 +80,8 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) */ len = simple_strtoul(argv[3], NULL, 16); if (len < fdt_totalsize(fdt)) { - printf ("New length %d < existing length %d, ignoring.\n", + printf ("New length %d < existing length %d, " + "ignoring.\n", len, fdt_totalsize(fdt)); } else { /* @@ -102,7 +89,8 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) */ err = fdt_open_into(fdt, fdt, len); if (err != 0) { - printf ("libfdt: %s\n", fdt_strerror(err)); + printf ("libfdt fdt_open_into(): %s\n", + fdt_strerror(err)); } } } @@ -110,12 +98,12 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /******************************************************************** * Move the fdt ********************************************************************/ - } else if (op == 'm') { + } else if ((argv[1][0] == 'm') && (argv[1][1] == 'o')) { struct fdt_header *newaddr; int len; int err; - if (argc != 5) { + if (argc < 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } @@ -128,12 +116,22 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - newaddr = (struct fdt_header *)simple_strtoul(argv[3], NULL, 16); - len = simple_strtoul(argv[4], NULL, 16); - if (len < fdt_totalsize(fdt)) { - printf ("New length %d < existing length %d, aborting.\n", - len, fdt_totalsize(fdt)); - return 1; + newaddr = (struct fdt_header *)simple_strtoul(argv[3],NULL,16); + + /* + * If the user specifies a length, use that. Otherwise use the + * current length. + */ + if (argc <= 4) { + len = fdt_totalsize(fdt); + } else { + len = simple_strtoul(argv[4], NULL, 16); + if (len < fdt_totalsize(fdt)) { + printf ("New length 0x%X < existing length " + "0x%X, aborting.\n", + len, fdt_totalsize(fdt)); + return 1; + } } /* @@ -141,26 +139,59 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) */ err = fdt_open_into(fdt, newaddr, len); if (err != 0) { - printf ("libfdt: %s\n", fdt_strerror(err)); + printf ("libfdt fdt_open_into(): %s\n", + fdt_strerror(err)); return 1; } fdt = newaddr; /******************************************************************** - * Set the value of a node in the fdt. + * Make a new node + ********************************************************************/ + } else if ((argv[1][0] == 'm') && (argv[1][1] == 'k')) { + char *pathp; /* path */ + char *nodep; /* new node to add */ + int nodeoffset; /* node offset from libfdt */ + int err; + + /* + * Parameters: Node path, new node to be appended to the path. + */ + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + pathp = argv[2]; + nodep = argv[3]; + + nodeoffset = fdt_find_node_by_path (fdt, pathp); + if (nodeoffset < 0) { + /* + * Not found or something else bad happened. + */ + printf ("libfdt fdt_find_node_by_path() returned %s\n", + fdt_strerror(nodeoffset)); + return 1; + } + err = fdt_add_subnode(fdt, nodeoffset, nodep); + if (err < 0) { + printf ("libfdt fdt_add_subnode(): %s\n", + fdt_strerror(err)); + return 1; + } + + /******************************************************************** + * Set the value of a property in the fdt. ********************************************************************/ - } else if (op == 's') { + } else if (argv[1][0] == 's') { char *pathp; /* path */ - char *prop; /* property */ - struct fdt_property *nodep; /* node struct pointer */ + char *prop; /* property */ char *newval; /* value from the user (as a string) */ - char *vp; /* temporary value pointer */ - char *cp; /* temporary char pointer */ int nodeoffset; /* node offset from libfdt */ - int len; /* new length of the property */ - int oldlen; /* original length of the property */ - unsigned long tmp; /* holds converted values */ - int ret; /* return value */ + static char data[SCRATCHPAD]; /* storage for the property */ + int len; /* new length of the property */ + int ret; /* return value */ /* * Parameters: Node path, property, value. @@ -174,121 +205,38 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) prop = argv[3]; newval = argv[4]; - if (strcmp(pathp, "/") == 0) { - nodeoffset = 0; - } else { - nodeoffset = fdt_path_offset (fdt, pathp); - if (nodeoffset < 0) { - /* - * Not found or something else bad happened. - */ - printf ("libfdt: %s\n", fdt_strerror(nodeoffset)); - return 1; - } - } - nodep = fdt_getprop (fdt, nodeoffset, prop, &oldlen); - if (oldlen < 0) { - printf ("libfdt %s\n", fdt_strerror(oldlen)); - return 1; - } else if (oldlen == 0) { + nodeoffset = fdt_find_node_by_path (fdt, pathp); + if (nodeoffset < 0) { /* - * The specified property has no value + * Not found or something else bad happened. */ - printf("%s has no value, cannot set one (yet).\n", prop); + printf ("libfdt fdt_find_node_by_path() returned %s\n", + fdt_strerror(nodeoffset)); return 1; - } else { - /* - * Convert the new property - */ - vp = data; - if (*newval == '<') { - /* - * Bigger values than bytes. - */ - len = 0; - newval++; - while ((*newval != '>') && (*newval != '\0')) { - cp = newval; - tmp = simple_strtoul(cp, &newval, 16); - if ((newval - cp) <= 2) { - *vp = tmp & 0xFF; - vp += 1; - len += 1; - } else if ((newval - cp) <= 4) { - *(uint16_t *)vp = __cpu_to_be16(tmp); - vp += 2; - len += 2; - } else if ((newval - cp) <= 8) { - *(uint32_t *)vp = __cpu_to_be32(tmp); - vp += 4; - len += 4; - } else { - printf("Sorry, I could not convert \"%s\"\n", cp); - return 1; - } - while (*newval == ' ') - newval++; - } - if (*newval != '>') { - printf("Unexpected character '%c'\n", *newval); - return 1; - } - } else if (*newval == '[') { - /* - * Byte stream. Convert the values. - */ - len = 0; - newval++; - while ((*newval != ']') && (*newval != '\0')) { - tmp = simple_strtoul(newval, &newval, 16); - *vp++ = tmp & 0xFF; - len++; - while (*newval == ' ') - newval++; - } - if (*newval != ']') { - printf("Unexpected character '%c'\n", *newval); - return 1; - } - } else { - /* - * Assume it is a string. Copy it into our data area for - * convenience (including the terminating '\0'). - */ - len = strlen(newval) + 1; - strcpy(data, newval); - } + } + ret = fdt_parse_prop(pathp, prop, newval, data, &len); + if (ret != 0) + return ret; - ret = fdt_setprop(fdt, nodeoffset, prop, data, len); - if (ret < 0) { - printf ("libfdt %s\n", fdt_strerror(ret)); - return 1; - } + ret = fdt_setprop(fdt, nodeoffset, prop, data, len); + if (ret < 0) { + printf ("libfdt fdt_setprop(): %s\n", fdt_strerror(ret)); + return 1; } /******************************************************************** * Print (recursive) / List (single level) ********************************************************************/ - } else if ((op == 'p') || (op == 'l')) { - /* - * Recursively print (a portion of) the fdt. - */ - static int offstack[MAX_LEVEL]; - static char tabs[MAX_LEVEL+1] = "\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t"; + } else if ((argv[1][0] == 'p') || (argv[1][0] == 'l')) { int depth = MAX_LEVEL; /* how deep to print */ char *pathp; /* path */ - char *prop; /* property */ - void *nodep; /* property node pointer */ - int nodeoffset; /* node offset from libfdt */ - int nextoffset; /* next node offset from libfdt */ - uint32_t tag; /* tag */ - int len; /* length of the property */ - int level = 0; /* keep track of nesting level */ + char *prop; /* property */ + int ret; /* return value */ /* * list is an alias for print, but limited to 1 level */ - if (op == 'l') { + if (argv[1][0] == 'l') { depth = 1; } @@ -302,99 +250,14 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) else prop = NULL; - if (strcmp(pathp, "/") == 0) { - nodeoffset = 0; - printf("/"); - } else { - nodeoffset = fdt_path_offset (fdt, pathp); - if (nodeoffset < 0) { - /* - * Not found or something else bad happened. - */ - printf ("libfdt %s\n", fdt_strerror(nodeoffset)); - return 1; - } - } - /* - * The user passed in a property as well as node path. Print only - * the given property and then return. - */ - if (prop) { - nodep = fdt_getprop (fdt, nodeoffset, prop, &len); - if (len == 0) { - printf("%s %s\n", pathp, prop); /* no property value */ - return 0; - } else if (len > 0) { - printf("%s=", prop); - print_data (nodep, len); - printf("\n"); - return 0; - } else { - printf ("libfdt %s\n", fdt_strerror(len)); - return 1; - } - } - - /* - * The user passed in a node path and no property, print the node - * and all subnodes. - */ - offstack[0] = nodeoffset; - - while(level >= 0) { - tag = fdt_next_tag(fdt, nodeoffset, &nextoffset, &pathp); - switch(tag) { - case FDT_BEGIN_NODE: - if(level <= depth) - printf("%s%s {\n", &tabs[MAX_LEVEL - level], pathp); - level++; - offstack[level] = nodeoffset; - if (level >= MAX_LEVEL) { - printf("Aaaiii <splat> nested too deep.\n"); - return 1; - } - break; - case FDT_END_NODE: - level--; - if(level <= depth) - printf("%s};\n", &tabs[MAX_LEVEL - level]); - if (level == 0) { - level = -1; /* exit the loop */ - } - break; - case FDT_PROP: - nodep = fdt_getprop (fdt, offstack[level], pathp, &len); - if (len < 0) { - printf ("libfdt %s\n", fdt_strerror(len)); - return 1; - } else if (len == 0) { - /* the property has no value */ - if(level <= depth) - printf("%s%s;\n", &tabs[MAX_LEVEL - level], pathp); - } else { - if(level <= depth) { - printf("%s%s=", &tabs[MAX_LEVEL - level], pathp); - print_data (nodep, len); - printf(";\n"); - } - } - break; - case FDT_NOP: - break; - case FDT_END: - return 1; - default: - if(level <= depth) - printf("Unknown tag 0x%08X\n", tag); - return 1; - } - nodeoffset = nextoffset; - } + ret = fdt_print(pathp, prop, depth); + if (ret != 0) + return ret; /******************************************************************** * Remove a property/node ********************************************************************/ - } else if (op == 'r') { + } else if (argv[1][0] == 'r') { int nodeoffset; /* node offset from libfdt */ int err; @@ -402,17 +265,14 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Get the path. The root node is an oddball, the offset * is zero and has no name. */ - if (strcmp(argv[2], "/") == 0) { - nodeoffset = 0; - } else { - nodeoffset = fdt_path_offset (fdt, argv[2]); - if (nodeoffset < 0) { - /* - * Not found or something else bad happened. - */ - printf ("libfdt %s\n", fdt_strerror(nodeoffset)); - return 1; - } + nodeoffset = fdt_find_node_by_path (fdt, argv[2]); + if (nodeoffset < 0) { + /* + * Not found or something else bad happened. + */ + printf ("libfdt fdt_find_node_by_path() returned %s\n", + fdt_strerror(nodeoffset)); + return 1; } /* * Do the delete. A fourth parameter means delete a property, @@ -421,39 +281,40 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (argc > 3) { err = fdt_delprop(fdt, nodeoffset, argv[3]); if (err < 0) { - printf("fdt_delprop libfdt: %s\n", fdt_strerror(err)); + printf("libfdt fdt_delprop(): %s\n", + fdt_strerror(err)); return err; } } else { err = fdt_del_node(fdt, nodeoffset); if (err < 0) { - printf("fdt_del_node libfdt: %s\n", fdt_strerror(err)); + printf("libfdt fdt_del_node(): %s\n", + fdt_strerror(err)); return err; } } - - /******************************************************************** - * Create a chosen node - ********************************************************************/ - } else if (op == 'c') { + } +#ifdef CONFIG_OF_BOARD_SETUP + /* Call the board-specific fixup routine */ + else if (argv[1][0] == 'b') + ft_board_setup(fdt, gd->bd); +#endif + /* Create a chosen node */ + else if (argv[1][0] == 'c') fdt_chosen(fdt, 0, 0, 1); - /******************************************************************** - * Create a u-boot-env node - ********************************************************************/ - } else if (op == 'e') { +#ifdef CONFIG_OF_HAS_UBOOT_ENV + /* Create a u-boot-env node */ + else if (argv[1][0] == 'e') fdt_env(fdt); - - /******************************************************************** - * Create a bd_t node - ********************************************************************/ - } else if (op == 'b') { +#endif +#ifdef CONFIG_OF_HAS_BD_T + /* Create a bd_t node */ + else if (argv[1][0] == 'b') fdt_bd_t(fdt); - - /******************************************************************** - * Unrecognized command - ********************************************************************/ - } else { +#endif + else { + /* Unrecognized command */ printf ("Usage:\n%s\n", cmdtp->usage); return 1; } @@ -461,7 +322,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } -/********************************************************************/ +/****************************************************************************/ static int fdt_valid(void) { @@ -477,19 +338,21 @@ static int fdt_valid(void) return 1; /* valid */ if (err < 0) { - printf("libfdt: %s", fdt_strerror(err)); + printf("libfdt fdt_check_header(): %s", fdt_strerror(err)); /* * Be more informative on bad version. */ if (err == -FDT_ERR_BADVERSION) { if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) { printf (" - too old, fdt $d < %d", - fdt_version(fdt), FDT_FIRST_SUPPORTED_VERSION); + fdt_version(fdt), + FDT_FIRST_SUPPORTED_VERSION); fdt = NULL; } if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) { printf (" - too new, fdt $d > %d", - fdt_version(fdt), FDT_LAST_SUPPORTED_VERSION); + fdt_version(fdt), + FDT_LAST_SUPPORTED_VERSION); fdt = NULL; } return 0; @@ -500,13 +363,91 @@ static int fdt_valid(void) return 1; } -/********************************************************************/ +/****************************************************************************/ /* - * OF flat tree handling - * Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com> - * Updated by: Matthew McClintock <msm@freescale.com> - * Converted to libfdt by: Gerald Van Baren <vanbaren@cideas.com> + * Parse the user's input, partially heuristic. Valid formats: + * <00> - hex byte + * <0011> - hex half word (16 bits) + * <00112233> - hex word (32 bits) + * - hex double words (64 bits) are not supported, must use + * a byte stream instead. + * [00 11 22 .. nn] - byte stream + * "string" - If the the value doesn't start with "<" or "[", it is + * treated as a string. Note that the quotes are + * stripped by the parser before we get the string. + */ +static int fdt_parse_prop(char *pathp, char *prop, char *newval, + char *data, int *len) +{ + char *cp; /* temporary char pointer */ + unsigned long tmp; /* holds converted values */ + + if (*newval == '<') { + /* + * Bigger values than bytes. + */ + *len = 0; + newval++; + while ((*newval != '>') && (*newval != '\0')) { + cp = newval; + tmp = simple_strtoul(cp, &newval, 16); + if ((newval - cp) <= 2) { + *data = tmp & 0xFF; + data += 1; + *len += 1; + } else if ((newval - cp) <= 4) { + *(uint16_t *)data = __cpu_to_be16(tmp); + data += 2; + *len += 2; + } else if ((newval - cp) <= 8) { + *(uint32_t *)data = __cpu_to_be32(tmp); + data += 4; + *len += 4; + } else { + printf("Sorry, I could not convert \"%s\"\n", + cp); + return 1; + } + while (*newval == ' ') + newval++; + } + if (*newval != '>') { + printf("Unexpected character '%c'\n", *newval); + return 1; + } + } else if (*newval == '[') { + /* + * Byte stream. Convert the values. + */ + *len = 0; + newval++; + while ((*newval != ']') && (*newval != '\0')) { + tmp = simple_strtoul(newval, &newval, 16); + *data++ = tmp & 0xFF; + *len = *len + 1; + while (*newval == ' ') + newval++; + } + if (*newval != ']') { + printf("Unexpected character '%c'\n", *newval); + return 1; + } + } else { + /* + * Assume it is a string. Copy it into our data area for + * convenience (including the terminating '\0'). + */ + *len = strlen(newval) + 1; + strcpy(data, newval); + } + return 0; +} + +/****************************************************************************/ + +/* + * Heuristic to guess if this is a string or concatenated strings. */ static int is_printable_string(const void *data, int len) @@ -546,6 +487,12 @@ static int is_printable_string(const void *data, int len) return 1; } + +/* + * Print the property in the best format, a heuristic guess. Print as + * a string, concatenated strings, a byte, word, double word, or (if all + * else fails) it is printed as a stream of bytes. + */ static void print_data(const void *data, int len) { int j; @@ -601,32 +548,146 @@ static void print_data(const void *data, int len) } } +/****************************************************************************/ + +/* + * Recursively print (a portion of) the fdt. The depth parameter + * determines how deeply nested the fdt is printed. + */ +static int fdt_print(char *pathp, char *prop, int depth) +{ + static int offstack[MAX_LEVEL]; + static char tabs[MAX_LEVEL+1] = + "\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t" + "\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t"; + void *nodep; /* property node pointer */ + int nodeoffset; /* node offset from libfdt */ + int nextoffset; /* next node offset from libfdt */ + uint32_t tag; /* tag */ + int len; /* length of the property */ + int level = 0; /* keep track of nesting level */ + + nodeoffset = fdt_find_node_by_path (fdt, pathp); + if (nodeoffset < 0) { + /* + * Not found or something else bad happened. + */ + printf ("libfdt fdt_find_node_by_path() returned %s\n", + fdt_strerror(nodeoffset)); + return 1; + } + /* + * The user passed in a property as well as node path. + * Print only the given property and then return. + */ + if (prop) { + nodep = fdt_getprop (fdt, nodeoffset, prop, &len); + if (len == 0) { + /* no property value */ + printf("%s %s\n", pathp, prop); + return 0; + } else if (len > 0) { + printf("%s=", prop); + print_data (nodep, len); + printf("\n"); + return 0; + } else { + printf ("libfdt fdt_getprop(): %s\n", + fdt_strerror(len)); + return 1; + } + } + + /* + * The user passed in a node path and no property, + * print the node and all subnodes. + */ + offstack[0] = nodeoffset; + + while(level >= 0) { + tag = fdt_next_tag(fdt, nodeoffset, &nextoffset, &pathp); + switch(tag) { + case FDT_BEGIN_NODE: + if(level <= depth) + printf("%s%s {\n", + &tabs[MAX_LEVEL - level], pathp); + level++; + offstack[level] = nodeoffset; + if (level >= MAX_LEVEL) { + printf("Aaaiii <splat> nested too deep. " + "Aborting.\n"); + return 1; + } + break; + case FDT_END_NODE: + level--; + if(level <= depth) + printf("%s};\n", &tabs[MAX_LEVEL - level]); + if (level == 0) { + level = -1; /* exit the loop */ + } + break; + case FDT_PROP: + nodep = fdt_getprop (fdt, offstack[level], pathp, &len); + if (len < 0) { + printf ("libfdt fdt_getprop(): %s\n", + fdt_strerror(len)); + return 1; + } else if (len == 0) { + /* the property has no value */ + if(level <= depth) + printf("%s%s;\n", + &tabs[MAX_LEVEL - level], + pathp); + } else { + if(level <= depth) { + printf("%s%s=", + &tabs[MAX_LEVEL - level], + pathp); + print_data (nodep, len); + printf(";\n"); + } + } + break; + case FDT_NOP: + break; + case FDT_END: + return 1; + default: + if(level <= depth) + printf("Unknown tag 0x%08X\n", tag); + return 1; + } + nodeoffset = nextoffset; + } + return 0; +} + /********************************************************************/ U_BOOT_CMD( fdt, 5, 0, do_fdt, "fdt - flattened device tree utility commands\n", "addr <addr> [<length>] - Set the fdt location to <addr>\n" +#ifdef CONFIG_OF_BOARD_SETUP + "fdt boardsetup - Do board-specific set up\n" +#endif "fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr>\n" "fdt print <path> [<prop>] - Recursive print starting at <path>\n" "fdt list <path> [<prop>] - Print one level starting at <path>\n" "fdt set <path> <prop> [<val>] - Set <property> [to <val>]\n" "fdt mknode <path> <node> - Create a new node after <path>\n" "fdt rm <path> [<prop>] - Delete the node or <property>\n" - "fdt chosen - Add/update the \"/chosen\" branch in the tree\n" + "fdt chosen - Add/update the /chosen branch in the tree\n" #ifdef CONFIG_OF_HAS_UBOOT_ENV - "fdt env - Add/replace the \"/u-boot-env\" branch in the tree\n" + "fdt env - Add/replace the /u-boot-env branch in the tree\n" #endif #ifdef CONFIG_OF_HAS_BD_T - "fdt bd_t - Add/replace the \"/bd_t\" branch in the tree\n" + "fdt bd_t - Add/replace the /bd_t branch in the tree\n" #endif "Hints:\n" - " * Set a larger length with the fdt addr command to add to the blob.\n" - " * If the property you are setting/printing has a '#' character,\n" - " you MUST escape it with a \\ character or quote it with \" or\n" - " it will be ignored as a comment.\n" - " * If the value has spaces in it, you MUST escape the spaces with\n" - " \\ characters or quote it with \"\"\n" + " If the property you are setting/printing has a '#' character or spaces,\n" + " you MUST escape it with a \\ character or quote it with \".\n" "Examples: fdt print / # print the whole tree\n" " fdt print /cpus \"#address-cells\"\n" " fdt set /cpus \"#address-cells\" \"[00 00 00 01]\"\n" diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index de5a514..1db0fc3 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -193,7 +193,12 @@ int _do_setenv (int flag, int argc, char *argv[]) * Ethernet Address and serial# can be set only once, * ver is readonly. */ +#ifdef CONFIG_HAS_UID + /* Allow serial# forced overwrite with 0xdeaf4add flag */ + if ( ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || +#else if ( (strcmp (name, "serial#") == 0) || +#endif ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) @@ -397,7 +402,15 @@ void setenv (char *varname, char *varvalue) _do_setenv (0, 3, argv); } -int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +#ifdef CONFIG_HAS_UID +void forceenv (char *varname, char *varvalue) +{ + char *argv[4] = { "forceenv", varname, varvalue, NULL }; + _do_setenv (0xdeaf4add, 3, argv); +} +#endif + +int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); diff --git a/common/fdt_support.c b/common/fdt_support.c index 69099c4..caaa682 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -37,6 +37,10 @@ */ DECLARE_GLOBAL_DATA_PTR; +/* + * fdt points to our working device tree. + */ +struct fdt_header *fdt; /********************************************************************/ @@ -45,13 +49,12 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) bd_t *bd = gd->bd; int nodeoffset; int err; - u32 tmp; /* used to set 32 bit integer properties */ - char *str; /* used to set string properties */ - ulong clock; + u32 tmp; /* used to set 32 bit integer properties */ + char *str; /* used to set string properties */ err = fdt_check_header(fdt); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("fdt_chosen: %s\n", fdt_strerror(err)); return err; } @@ -63,11 +66,12 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) err = fdt_num_reservemap(fdt, &used, &total); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("fdt_chosen: %s\n", fdt_strerror(err)); return err; } if (used >= total) { - printf("fdt_chosen: no room in the reserved map (%d of %d)\n", + printf("WARNING: " + "no room in the reserved map (%d of %d)\n", used, total); return -1; } @@ -84,7 +88,7 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) err = fdt_replace_reservemap_entry(fdt, j, initrd_start, initrd_end - initrd_start + 1); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("fdt_chosen: %s\n", fdt_strerror(err)); return err; } } @@ -92,7 +96,7 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) /* * Find the "chosen" node. */ - nodeoffset = fdt_path_offset (fdt, "/chosen"); + nodeoffset = fdt_find_node_by_path (fdt, "/chosen"); /* * If we have a "chosen" node already the "force the writing" @@ -110,7 +114,8 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) */ nodeoffset = fdt_add_subnode(fdt, 0, "chosen"); if (nodeoffset < 0) { - printf("libfdt: %s\n", fdt_strerror(nodeoffset)); + printf("WARNING: could not create /chosen %s.\n", + fdt_strerror(nodeoffset)); return nodeoffset; } } @@ -120,42 +125,35 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) */ str = getenv("bootargs"); if (str != NULL) { - err = fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str)+1); + err = fdt_setprop(fdt, nodeoffset, + "bootargs", str, strlen(str)+1); if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); + printf("WARNING: could not set bootargs %s.\n", + fdt_strerror(err)); } if (initrd_start && initrd_end) { tmp = __cpu_to_be32(initrd_start); - err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp)); + err = fdt_setprop(fdt, nodeoffset, + "linux,initrd-start", &tmp, sizeof(tmp)); if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); + printf("WARNING: " + "could not set linux,initrd-start %s.\n", + fdt_strerror(err)); tmp = __cpu_to_be32(initrd_end); - err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp)); + err = fdt_setprop(fdt, nodeoffset, + "linux,initrd-end", &tmp, sizeof(tmp)); if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); + printf("WARNING: could not set linux,initrd-end %s.\n", + fdt_strerror(err)); } #ifdef OF_STDOUT_PATH - err = fdt_setprop(fdt, nodeoffset, "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1); + err = fdt_setprop(fdt, nodeoffset, + "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1); if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); + printf("WARNING: could not set linux,stdout-path %s.\n", + fdt_strerror(err)); #endif - nodeoffset = fdt_path_offset (fdt, "/cpus"); - if (nodeoffset >= 0) { - clock = cpu_to_be32(bd->bi_intfreq); - err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - } -#ifdef OF_TBCLK - nodeoffset = fdt_path_offset (fdt, "/cpus/" OF_CPU "/timebase-frequency"); - if (nodeoffset >= 0) { - clock = cpu_to_be32(OF_TBCLK); - err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - } -#endif return err; } @@ -177,7 +175,7 @@ int fdt_env(void *fdt) err = fdt_check_header(fdt); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("fdt_env: %s\n", fdt_strerror(err)); return err; } @@ -185,11 +183,11 @@ int fdt_env(void *fdt) * See if we already have a "u-boot-env" node, delete it if so. * Then create a new empty node. */ - nodeoffset = fdt_path_offset (fdt, "/u-boot-env"); + nodeoffset = fdt_find_node_by_path (fdt, "/u-boot-env"); if (nodeoffset >= 0) { err = fdt_del_node(fdt, nodeoffset); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("fdt_env: %s\n", fdt_strerror(err)); return err; } } @@ -198,7 +196,8 @@ int fdt_env(void *fdt) */ nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env"); if (nodeoffset < 0) { - printf("libfdt: %s\n", fdt_strerror(nodeoffset)); + printf("WARNING: could not create /u-boot-env %s.\n", + fdt_strerror(nodeoffset)); return nodeoffset; } @@ -226,7 +225,8 @@ int fdt_env(void *fdt) continue; err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("WARNING: could not set %s %s.\n", + lval, fdt_strerror(err)); return err; } } @@ -292,12 +292,12 @@ int fdt_bd_t(void *fdt) bd_t *bd = gd->bd; int nodeoffset; int err; - u32 tmp; /* used to set 32 bit integer properties */ + u32 tmp; /* used to set 32 bit integer properties */ int i; err = fdt_check_header(fdt); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("fdt_bd_t: %s\n", fdt_strerror(err)); return err; } @@ -305,11 +305,11 @@ int fdt_bd_t(void *fdt) * See if we already have a "bd_t" node, delete it if so. * Then create a new empty node. */ - nodeoffset = fdt_path_offset (fdt, "/bd_t"); + nodeoffset = fdt_find_node_by_path (fdt, "/bd_t"); if (nodeoffset >= 0) { err = fdt_del_node(fdt, nodeoffset); if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); + printf("fdt_bd_t: %s\n", fdt_strerror(err)); return err; } } @@ -318,7 +318,9 @@ int fdt_bd_t(void *fdt) */ nodeoffset = fdt_add_subnode(fdt, 0, "bd_t"); if (nodeoffset < 0) { - printf("libfdt: %s\n", fdt_strerror(nodeoffset)); + printf("WARNING: could not create /bd_t %s.\n", + fdt_strerror(nodeoffset)); + printf("fdt_bd_t: %s\n", fdt_strerror(nodeoffset)); return nodeoffset; } /* @@ -326,20 +328,23 @@ int fdt_bd_t(void *fdt) */ for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) { tmp = cpu_to_be32(getenv("bootargs")); - err = fdt_setprop(fdt, nodeoffset, bd_map[i].name, &tmp, sizeof(tmp)); + err = fdt_setprop(fdt, nodeoffset, + bd_map[i].name, &tmp, sizeof(tmp)); if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); + printf("WARNING: could not set %s %s.\n", + bd_map[i].name, fdt_strerror(err)); } /* * Add a couple of oddball entries... */ err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6); if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); + printf("WARNING: could not set enetaddr %s.\n", + fdt_strerror(err)); err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4); if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - + printf("WARNING: could not set ethspeed %s.\n", + fdt_strerror(err)); return 0; } #endif /* ifdef CONFIG_OF_HAS_BD_T */ diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile new file mode 100644 index 0000000..0f77f40 --- /dev/null +++ b/cpu/arm926ejs/davinci/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o +SOBJS = lowlevel_init.o reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c new file mode 100644 index 0000000..5719845 --- /dev/null +++ b/cpu/arm926ejs/davinci/dp83848.c @@ -0,0 +1,156 @@ +/* + * National Semiconductor DP83848 PHY Driver for TI DaVinci + * (TMS320DM644x) based boards. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <net.h> +#include <dp83848.h> +#include <asm/arch/emac_defs.h> + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +int dp83848_is_phy_connected(int phy_addr) +{ + u_int16_t id1, id2; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) + return(0); + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) + return(0); + + if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI)) + return(1); + + return(0); +} + +int dp83848_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_LINK_STATUS)) /* link up? */ + return(0); + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) + return(0); + + /* Speed doesn't matter, there is no setting for it in EMAC... */ + if (tmp & DP83848_SPEED) { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } else { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } + + return(0); +} + + +int dp83848_init_phy(int phy_addr) +{ + int ret = 1; + + if (!dp83848_get_link_speed(phy_addr)) { + /* Try another time */ + udelay(100000); + ret = dp83848_get_link_speed(phy_addr); + } + + /* Disable PHY Interrupts */ + dm644x_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); + + return(ret); +} + + +int dp83848_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */ + tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */ + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Set the Auto_negotiation Advertisement Register + * MII advertising for Next page, 100BaseTxFD and HD, + * 10BaseTFD and HD, IEEE 802.3 + */ + tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | + DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; + dm644x_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); + + + /* Read Control Register */ + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Restart Auto_negotiation */ + tmp |= DP83848_RESTART_AUTONEG; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /*check AutoNegotiate complete */ + udelay(10000); + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_AUTONEG_COMP)) + return(0); + + return (dp83848_get_link_speed(phy_addr)); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c new file mode 100644 index 0000000..766bc7d --- /dev/null +++ b/cpu/arm926ejs/davinci/ether.c @@ -0,0 +1,650 @@ +/* + * Ethernet driver for TI TMS320DM644x (DaVinci) chips. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright + * follows: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.c + * + * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. + * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors + * + */ +#include <common.h> +#include <command.h> +#include <net.h> +#include <miiphy.h> +#include <asm/arch/emac_defs.h> + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +unsigned int emac_dbg = 0; +#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) + +/* Internal static functions */ +static int dm644x_eth_hw_init (void); +static int dm644x_eth_open (void); +static int dm644x_eth_close (void); +static int dm644x_eth_send_packet (volatile void *packet, int length); +static int dm644x_eth_rcv_packet (void); +static void dm644x_eth_mdio_enable(void); + +static int gen_init_phy(int phy_addr); +static int gen_is_phy_connected(int phy_addr); +static int gen_get_link_speed(int phy_addr); +static int gen_auto_negotiate(int phy_addr); + +/* Wrappers exported to the U-Boot proper */ +int eth_hw_init(void) +{ + return(dm644x_eth_hw_init()); +} + +int eth_init(bd_t * bd) +{ + return(dm644x_eth_open()); +} + +void eth_halt(void) +{ + dm644x_eth_close(); +} + +int eth_send(volatile void *packet, int length) +{ + return(dm644x_eth_send_packet(packet, length)); +} + +int eth_rx(void) +{ + return(dm644x_eth_rcv_packet()); +} + +void eth_mdio_enable(void) +{ + dm644x_eth_mdio_enable(); +} +/* End of wrappers */ + + +static u_int8_t dm644x_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + +/* + * This function must be called before emac_open() if you want to override + * the default mac address. + */ +void dm644x_eth_set_mac_addr(const u_int8_t *addr) +{ + int i; + + for (i = 0; i < sizeof (dm644x_eth_mac_addr); i++) { + dm644x_eth_mac_addr[i] = addr[i]; + } +} + +/* EMAC Addresses */ +static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; +static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; +static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; + +/* EMAC descriptors */ +static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); +static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +static volatile emac_desc *emac_rx_active_head = 0; +static volatile emac_desc *emac_rx_active_tail = 0; +static int emac_rx_queue_active = 0; + +/* Receive packet buffers */ +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + +/* PHY address for a discovered PHY (0xff - not found) */ +static volatile u_int8_t active_phy_addr = 0xff; + +phy_t phy; + +static void dm644x_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + adap_mdio->CONTROL = (clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE; + + while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} +} + +/* + * Tries to find an active connected PHY. Returns 1 if address if found. + * If no active PHY (or more than one PHY) found returns 0. + * Sets active_phy_addr variable. + */ +static int dm644x_eth_phy_detect(void) +{ + u_int32_t phy_act_state; + int i; + + active_phy_addr = 0xff; + + if ((phy_act_state = adap_mdio->ALIVE) == 0) + return(0); /* No active PHYs */ + + debug_emac("dm644x_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); + + for (i = 0; i < 32; i++) { + if (phy_act_state & (1 << i)) { + if (phy_act_state & ~(1 << i)) + return(0); /* More than one PHY */ + else { + active_phy_addr = i; + return(1); + } + } + } + + return(0); /* Just to make GCC happy */ +} + + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16); + + /* Wait for command to complete */ + while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return(1); + } + + *data = -1; + return(0); +} + +/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff); + + /* Wait for command to complete */ + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + return(1); +} + +/* PHY functions for a generic PHY */ +static int gen_init_phy(int phy_addr) +{ + int ret = 1; + + if (gen_get_link_speed(phy_addr)) { + /* Try another time */ + ret = gen_get_link_speed(phy_addr); + } + + return(ret); +} + +static int gen_is_phy_connected(int phy_addr) +{ + u_int16_t dummy; + + return(dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); +} + +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if (dm644x_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) + return(1); + + return(0); +} + +static int gen_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_BMCR_AUTON; + dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + return(0); + + if (!(tmp & PHY_BMSR_AUTN_COMP)) + return(0); + + return(gen_get_link_speed(phy_addr)); +} +/* End of generic PHY functions */ + + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) +{ + return(dm644x_eth_phy_read(addr, reg, value) ? 0 : 1); +} + +static int dm644x_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value) +{ + return(dm644x_eth_phy_write(addr, reg, value) ? 0 : 1); +} + +int dm644x_eth_miiphy_initialize(bd_t *bis) +{ + miiphy_register(phy.name, dm644x_mii_phy_read, dm644x_mii_phy_write); + + return(1); +} +#endif + +/* + * This function initializes the emac hardware. It does NOT initialize + * EMAC modules power or pin multiplexors, that is done by board_init() + * much earlier in bootup process. Returns 1 on success, 0 otherwise. + */ +static int dm644x_eth_hw_init(void) +{ + u_int32_t phy_id; + u_int16_t tmp; + int i; + + dm644x_eth_mdio_enable(); + + for (i = 0; i < 256; i++) { + if (adap_mdio->ALIVE) + break; + udelay(10); + } + + if (i >= 256) { + printf("No ETH PHY detected!!!\n"); + return(0); + } + + /* Find if a PHY is connected and get it's address */ + if (!dm644x_eth_phy_detect()) + return(0); + + /* Get PHY ID and initialize phy_ops for a detected PHY */ + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id = (tmp << 16) & 0xffff0000; + + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id |= tmp & 0x0000ffff; + + switch (phy_id) { + case PHY_LXT972: + sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); + phy.init = lxt972_init_phy; + phy.is_phy_connected = lxt972_is_phy_connected; + phy.get_link_speed = lxt972_get_link_speed; + phy.auto_negotiate = lxt972_auto_negotiate; + break; + case PHY_DP83848: + sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); + phy.init = dp83848_init_phy; + phy.is_phy_connected = dp83848_is_phy_connected; + phy.get_link_speed = dp83848_get_link_speed; + phy.auto_negotiate = dp83848_auto_negotiate; + break; + default: + sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); + phy.init = gen_init_phy; + phy.is_phy_connected = gen_is_phy_connected; + phy.get_link_speed = gen_get_link_speed; + phy.auto_negotiate = gen_auto_negotiate; + } + + return(1); +} + + +/* Eth device open */ +static int dm644x_eth_open(void) +{ + dv_reg_p addr; + u_int32_t clkdiv, cnt; + volatile emac_desc *rx_desc; + + debug_emac("+ emac_open\n"); + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + while (adap_emac->SOFTRESET != 0) {;} + adap_ewrap->EWCTL = 0; + for (cnt = 0; cnt < 5; cnt++) { + clkdiv = adap_ewrap->EWCTL; + } + + rx_desc = emac_rx_desc; + + adap_emac->TXCONTROL = 0x01; + adap_emac->RXCONTROL = 0x01; + + /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ + /* Using channel 0 only - other channels are disabled */ + adap_emac->MACINDEX = 0; + adap_emac->MACADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACADDRLO = + (dm644x_eth_mac_addr[5] << 8) | + (dm644x_eth_mac_addr[4]); + + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Set source MAC address - REQUIRED */ + adap_emac->MACSRCADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACSRCADDRLO = + (dm644x_eth_mac_addr[4] << 8) | + (dm644x_eth_mac_addr[5]); + + /* Set DMA 8 TX / 8 RX Head pointers to 0 */ + addr = &adap_emac->TX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + addr = &adap_emac->RX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + /* Clear Statistics (do this before setting MacControl register) */ + addr = &adap_emac->RXGOODFRAMES; + for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) + *addr++ = 0; + + /* No multicast addressing */ + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Create RX queue and set receive process in place */ + emac_rx_active_head = emac_rx_desc; + for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { + rx_desc->next = (u_int32_t)(rx_desc + 1); + rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_desc++; + } + + /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ + rx_desc--; + rx_desc->next = 0; + emac_rx_active_tail = rx_desc; + emac_rx_queue_active = 1; + + /* Enable TX/RX */ + adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; + adap_emac->RXBUFFEROFFSET = 0; + + /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ + adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; + + /* Enable ch 0 only */ + adap_emac->RXUNICASTSET = 0x01; + + /* Enable MII interface and Full duplex mode */ + adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); + + /* Init MDIO & get link state */ + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); + + if (!phy.get_link_speed(active_phy_addr)) + return(0); + + /* Start receive process */ + adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; + + debug_emac("- emac_open\n"); + + return(1); +} + +/* EMAC Channel Teardown */ +static void dm644x_eth_ch_teardown(int ch) +{ + dv_reg dly = 0xff; + dv_reg cnt; + + debug_emac("+ emac_ch_teardown\n"); + + if (ch == EMAC_CH_TX) { + /* Init TX channel teardown */ + adap_emac->TXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { + /* Wait here for Tx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->TX0CP = cnt; + adap_emac->TX0HDP = 0; + } else { + /* Init RX channel teardown */ + adap_emac->RXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { + /* Wait here for Rx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->RX0CP = cnt; + adap_emac->RX0HDP = 0; + } + + debug_emac("- emac_ch_teardown\n"); +} + +/* Eth device close */ +static int dm644x_eth_close(void) +{ + debug_emac("+ emac_close\n"); + + dm644x_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ + dm644x_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + adap_ewrap->EWCTL = 0; + + debug_emac("- emac_close\n"); + return(1); +} + +static int tx_send_loop = 0; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int dm644x_eth_send_packet(volatile void *packet, int length) +{ + int ret_status = -1; + tx_send_loop = 0; + + /* Return error if no link */ + if (!phy.get_link_speed(active_phy_addr)) + { + printf("WARN: emac_send_packet: No link\n"); + return (ret_status); + } + + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) + { + length = EMAC_MIN_ETHERNET_PKT_SIZE; + } + + /* Populate the TX descriptor */ + emac_tx_desc->next = 0; + emac_tx_desc->buffer = (u_int8_t *)packet; + emac_tx_desc->buff_off_len = (length & 0xffff); + emac_tx_desc->pkt_flag_len = ((length & 0xffff) | + EMAC_CPPI_SOP_BIT | + EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT); + /* Send the packet */ + adap_emac->TX0HDP = (unsigned int)emac_tx_desc; + + /* Wait for packet to complete or link down */ + while (1) { + if (!phy.get_link_speed(active_phy_addr)) { + dm644x_eth_ch_teardown(EMAC_CH_TX); + return (ret_status); + } + if (adap_emac->TXINTSTATRAW & 0x01) { + ret_status = length; + break; + } + tx_send_loop++; + } + + return(ret_status); +} + +/* + * This function handles receipt of a packet from the network + */ +static int dm644x_eth_rcv_packet(void) +{ + volatile emac_desc *rx_curr_desc; + volatile emac_desc *curr_desc; + volatile emac_desc *tail_desc; + int status, ret = -1; + + rx_curr_desc = emac_rx_active_head; + status = rx_curr_desc->pkt_flag_len; + if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if (status & EMAC_CPPI_RX_ERROR_FRAME) { + /* Error in packet - discard it and requeue desc */ + printf("WARN: emac_rcv_pkt: Error in packet\n"); + } else { + NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); + ret = rx_curr_desc->buff_off_len & 0xffff; + } + + /* Ack received packet descriptor */ + adap_emac->RX0CP = (unsigned int)rx_curr_desc; + curr_desc = rx_curr_desc; + emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next; + + if (status & EMAC_CPPI_EOQ_BIT) { + if (emac_rx_active_head) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + } else { + emac_rx_queue_active = 0; + printf("INFO:emac_rcv_packet: RX Queue not active\n"); + } + } + + /* Recycle RX descriptor */ + rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_curr_desc->next = 0; + + if (emac_rx_active_head == 0) { + printf("INFO: emac_rcv_pkt: active queue head = 0\n"); + emac_rx_active_head = curr_desc; + emac_rx_active_tail = curr_desc; + if (emac_rx_queue_active != 0) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); + emac_rx_queue_active = 1; + } + } else { + tail_desc = emac_rx_active_tail; + emac_rx_active_tail = curr_desc; + tail_desc->next = (unsigned int)curr_desc; + status = tail_desc->pkt_flag_len; + if (status & EMAC_CPPI_EOQ_BIT) { + adap_emac->RX0HDP = (unsigned int)curr_desc; + status &= ~EMAC_CPPI_EOQ_BIT; + tail_desc->pkt_flag_len = status; + } + } + return(ret); + } + return(0); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c new file mode 100644 index 0000000..af9dc03 --- /dev/null +++ b/cpu/arm926ejs/davinci/i2c.c @@ -0,0 +1,351 @@ +/* + * TI DaVinci (TMS320DM644x) I2C driver. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CONFIG_DRIVER_DAVINCI_I2C + +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/i2c_defs.h> + +#define CHECK_NACK() \ + do {\ + if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ + REG(I2C_CON) = 0;\ + return(1);\ + }\ + } while (0) + + +static int wait_for_bus(void) +{ + int stat, timeout; + + REG(I2C_STAT) = 0xffff; + + for (timeout = 0; timeout < 10; timeout++) { + if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { + REG(I2C_STAT) = 0xffff; + return(0); + } + + REG(I2C_STAT) = stat; + udelay(50000); + } + + REG(I2C_STAT) = 0xffff; + return(1); +} + + +static int poll_i2c_irq(int mask) +{ + int stat, timeout; + + for (timeout = 0; timeout < 10; timeout++) { + udelay(1000); + stat = REG(I2C_STAT); + if (stat & mask) { + return(stat); + } + } + + REG(I2C_STAT) = 0xffff; + return(stat | I2C_TIMEOUT); +} + + +void flush_rx(void) +{ + int dummy; + + while (1) { + if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) + break; + + dummy = REG(I2C_DRR); + REG(I2C_STAT) = I2C_STAT_RRDY; + udelay(1000); + } +} + + +void i2c_init(int speed, int slaveadd) +{ + u_int32_t div, psc; + + if (REG(I2C_CON) & I2C_CON_EN) { + REG(I2C_CON) = 0; + udelay (50000); + } + + psc = 2; + div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ + REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ + REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ + REG(I2C_SCLH) = div - REG(I2C_SCLL); + + REG(I2C_OA) = slaveadd; + REG(I2C_CNT) = 0; + + /* Interrupts must be enabled or I2C module won't work */ + REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | + I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; + + /* Now enable I2C controller (get it out of reset) */ + REG(I2C_CON) = I2C_CON_EN; + + udelay(1000); +} + + +int i2c_probe(u_int8_t chip) +{ + int rc = 1; + + if (chip == REG(I2C_OA)) { + return(rc); + } + + REG(I2C_CON) = 0; + if (wait_for_bus()) {return(1);} + + /* try to read one byte from current (or only) address */ + REG(I2C_CNT) = 1; + REG(I2C_SA) = chip; + REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); + udelay (50000); + + if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { + rc = 0; + flush_rx(); + REG(I2C_STAT) = 0xffff; + } else { + REG(I2C_STAT) = 0xffff; + REG(I2C_CON) |= I2C_CON_STP; + udelay(20000); + if (wait_for_bus()) {return(1);} + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + return(rc); +} + + +int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + + if (wait_for_bus()) {return(1);} + + if (alen != 0) { + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; + REG(I2C_CNT) = alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + switch (alen) { + case 2: + /* Send address MSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + /* No break, fall through */ + case 1: + /* Send address LSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_ARDY)) { + REG(I2C_CON) = 0; + return(1); + } + } + } + + /* Address phase is over, now read 'len' bytes and stop */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; + REG(I2C_CNT) = len & 0xffff; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); + + CHECK_NACK(); + + if (tmp & I2C_STAT_RRDY) { + buf[i] = REG(I2C_DRR); + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + if (len < 0) { + printf("%s(): bogus length %x\n", __FUNCTION__, len); + return(1); + } + + if (wait_for_bus()) {return(1);} + + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; + REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + switch (alen) { + case 2: + /* Send address MSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + /* No break, fall through */ + case 1: + /* Send address LSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = buf[i]; + } else { + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg) +{ + u_int8_t tmp; + + i2c_read(chip, reg, 1, &tmp, 1); + return(tmp); +} + + +void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val) +{ + u_int8_t tmp; + + i2c_write(chip, reg, 1, &tmp, 1); +} + +#endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S new file mode 100644 index 0000000..a87c112 --- /dev/null +++ b/cpu/arm926ejs/davinci/lowlevel_init.S @@ -0,0 +1,707 @@ +/* + * Low-level board setup code for TI DaVinci SoC based boards. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Partially based on TI sources, original copyrights follow: + */ + +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, <www.ti.com> + * Kshitij Gupta <Kshitij@ti.com> + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Swaminathan S, Nov 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.globl lowlevel_init +lowlevel_init: + + /*-------------------------------------------------------* + * Mask all IRQs by setting all bits in the EINT default * + *-------------------------------------------------------*/ + mov r1, $0 + ldr r0, =EINT_ENABLE0 + str r1, [r0] + ldr r0, =EINT_ENABLE1 + str r1, [r0] + + /*------------------------------------------------------* + * Put the GEM in reset * + *------------------------------------------------------*/ + + /* Put the GEM in reset */ + ldr r8, PSC_GEM_FLAG_CLEAR + ldr r6, MDCTL_GEM + ldr r7, [r6] + and r7, r7, r8 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x02 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStopGem: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x02 + bne checkStatClkStopGem + + /* Check for GEM Reset Completion */ +checkGemStatClkStop: + ldr r6, MDSTAT_GEM + ldr r7, [r6] + ands r7, r7, $0x100 + bne checkGemStatClkStop + + /* Do this for enabling a WDT initiated reset this is a workaround + for a chip bug. Not required under normal situations */ + ldr r6, P1394 + mov r10, $0 + str r10, [r6] + + /*------------------------------------------------------* + * Enable L1 & L2 Memories in Fast mode * + *------------------------------------------------------*/ + ldr r6, DFT_ENABLE + mov r10, $0x01 + str r10, [r6] + + ldr r6, MMARG_BRF0 + ldr r10, MMARG_BRF0_VAL + str r10, [r6] + + ldr r6, DFT_ENABLE + mov r10, $0 + str r10, [r6] + + /*------------------------------------------------------* + * DDR2 PLL Initialization * + *------------------------------------------------------*/ + + /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ + mov r10, $0 + ldr r6, PLL2_CTL + ldr r7, PLL_CLKSRC_MASK + ldr r8, [r6] + and r8, r8, r7 + mov r9, r10, lsl $8 + orr r8, r8, r9 + str r8, [r6] + + /* Select the PLLEN source */ + ldr r7, PLL_ENSRC_MASK + and r8, r8, r7 + str r8, [r6] + + /* Bypass the PLL */ + ldr r7, PLL_BYPASS_MASK + and r8, r8, r7 + str r8, [r6] + + /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ + mov r10, $0x20 +WaitPPL2Loop: + subs r10, r10, $1 + bne WaitPPL2Loop + + /* Reset the PLL */ + ldr r7, PLL_RESET_MASK + and r8, r8, r7 + str r8, [r6] + + /* Power up the PLL */ + ldr r7, PLL_PWRUP_MASK + and r8, r8, r7 + str r8, [r6] + + /* Enable the PLL from Disable Mode */ + ldr r7, PLL_DISABLE_ENABLE_MASK + and r8, r8, r7 + str r8, [r6] + + /* Program the PLL Multiplier */ + ldr r6, PLL2_PLLM + mov r2, $0x17 /* 162 MHz */ + str r2, [r6] + + /* Program the PLL2 Divisor Value */ + ldr r6, PLL2_DIV2 + mov r3, $0x01 + str r3, [r6] + + /* Program the PLL2 Divisor Value */ + ldr r6, PLL2_DIV1 + mov r4, $0x0b /* 54 MHz */ + str r4, [r6] + + /* PLL2 DIV2 MMR */ + ldr r8, PLL2_DIV_MASK + ldr r6, PLL2_DIV2 + ldr r9, [r6] + and r8, r8, r9 + mov r9, $0x01 + mov r9, r9, lsl $15 + orr r8, r8, r9 + str r8, [r6] + + /* Program the GOSET bit to take new divider values */ + ldr r6, PLL2_PLLCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Wait for Done */ + ldr r6, PLL2_PLLSTAT +doneLoop_0: + ldr r7, [r6] + ands r7, r7, $0x01 + bne doneLoop_0 + + /* PLL2 DIV1 MMR */ + ldr r8, PLL2_DIV_MASK + ldr r6, PLL2_DIV1 + ldr r9, [r6] + and r8, r8, r9 + mov r9, $0x01 + mov r9, r9, lsl $15 + orr r8, r8, r9 + str r8, [r6] + + /* Program the GOSET bit to take new divider values */ + ldr r6, PLL2_PLLCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Wait for Done */ + ldr r6, PLL2_PLLSTAT +doneLoop: + ldr r7, [r6] + ands r7, r7, $0x01 + bne doneLoop + + /* Wait for PLL to Reset Properly */ + mov r10, $0x218 +ResetPPL2Loop: + subs r10, r10, $1 + bne ResetPPL2Loop + + /* Bring PLL out of Reset */ + ldr r6, PLL2_CTL + ldr r8, [r6] + orr r8, r8, $0x08 + str r8, [r6] + + /* Wait for PLL to Lock */ + ldr r10, PLL_LOCK_COUNT +PLL2Lock: + subs r10, r10, $1 + bne PLL2Lock + + /* Enable the PLL */ + ldr r6, PLL2_CTL + ldr r8, [r6] + orr r8, r8, $0x01 + str r8, [r6] + + /*------------------------------------------------------* + * Issue Soft Reset to DDR Module * + *------------------------------------------------------*/ + + /* Shut down the DDR2 LPSC Module */ + ldr r8, PSC_FLAG_CLEAR + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + and r7, r7, r8 + orr r7, r7, $0x03 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStop: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkStop + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkStop: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x03 + bne checkDDRStatClkStop + + /*------------------------------------------------------* + * Program DDR2 MMRs for 162MHz Setting * + *------------------------------------------------------*/ + + /* Program PHY Control Register */ + ldr r6, DDRCTL + ldr r7, DDRCTL_VAL + str r7, [r6] + + /* Program SDRAM Bank Config Register */ + ldr r6, SDCFG + ldr r7, SDCFG_VAL + str r7, [r6] + + /* Program SDRAM TIM-0 Config Register */ + ldr r6, SDTIM0 + ldr r7, SDTIM0_VAL_162MHz + str r7, [r6] + + /* Program SDRAM TIM-1 Config Register */ + ldr r6, SDTIM1 + ldr r7, SDTIM1_VAL_162MHz + str r7, [r6] + + /* Program the SDRAM Bank Config Control Register */ + ldr r10, MASK_VAL + ldr r8, SDCFG + ldr r9, SDCFG_VAL + and r9, r9, r10 + str r9, [r8] + + /* Program SDRAM SDREF Config Register */ + ldr r6, SDREF + ldr r7, SDREF_VAL + str r7, [r6] + + /*------------------------------------------------------* + * Issue Soft Reset to DDR Module * + *------------------------------------------------------*/ + + /* Issue a Dummy DDR2 read/write */ + ldr r8, DDR2_START_ADDR + ldr r7, DUMMY_VAL + str r7, [r8] + ldr r7, [r8] + + /* Shut down the DDR2 LPSC Module */ + ldr r8, PSC_FLAG_CLEAR + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + and r7, r7, r8 + orr r7, r7, $0x01 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStop2: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkStop2 + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkStop2: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x01 + bne checkDDRStatClkStop2 + + /*------------------------------------------------------* + * Turn DDR2 Controller Clocks On * + *------------------------------------------------------*/ + + /* Enable the DDR2 LPSC Module */ + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + orr r7, r7, $0x03 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkEn2: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkEn2 + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkEn2: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x03 + bne checkDDRStatClkEn2 + + /* DDR Writes and Reads */ + ldr r6, CFGTEST + mov r3, $0x01 + str r3, [r6] + + /*------------------------------------------------------* + * System PLL Initialization * + *------------------------------------------------------*/ + + /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ + mov r2, $0 + ldr r6, PLL1_CTL + ldr r7, PLL_CLKSRC_MASK + ldr r8, [r6] + and r8, r8, r7 + mov r9, r2, lsl $8 + orr r8, r8, r9 + str r8, [r6] + + /* Select the PLLEN source */ + ldr r7, PLL_ENSRC_MASK + and r8, r8, r7 + str r8, [r6] + + /* Bypass the PLL */ + ldr r7, PLL_BYPASS_MASK + and r8, r8, r7 + str r8, [r6] + + /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ + mov r10, $0x20 + +WaitLoop: + subs r10, r10, $1 + bne WaitLoop + + /* Reset the PLL */ + ldr r7, PLL_RESET_MASK + and r8, r8, r7 + str r8, [r6] + + /* Disable the PLL */ + orr r8, r8, $0x10 + str r8, [r6] + + /* Power up the PLL */ + ldr r7, PLL_PWRUP_MASK + and r8, r8, r7 + str r8, [r6] + + /* Enable the PLL from Disable Mode */ + ldr r7, PLL_DISABLE_ENABLE_MASK + and r8, r8, r7 + str r8, [r6] + + /* Program the PLL Multiplier */ + ldr r6, PLL1_PLLM + mov r3, $0x15 /* For 594MHz */ + str r3, [r6] + + /* Wait for PLL to Reset Properly */ + mov r10, $0xff + +ResetLoop: + subs r10, r10, $1 + bne ResetLoop + + /* Bring PLL out of Reset */ + ldr r6, PLL1_CTL + orr r8, r8, $0x08 + str r8, [r6] + + /* Wait for PLL to Lock */ + ldr r10, PLL_LOCK_COUNT + +PLL1Lock: + subs r10, r10, $1 + bne PLL1Lock + + /* Enable the PLL */ + orr r8, r8, $0x01 + str r8, [r6] + + nop + nop + nop + nop + + /*------------------------------------------------------* + * AEMIF configuration for NOR Flash (double check) * + *------------------------------------------------------*/ + ldr r0, _PINMUX0 + ldr r1, _DEV_SETTING + str r1, [r0] + + ldr r0, WAITCFG + ldr r1, WAITCFG_VAL + ldr r2, [r0] + orr r2, r2, r1 + str r2, [r0] + + ldr r0, ACFG3 + ldr r1, ACFG3_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + ldr r0, ACFG4 + ldr r1, ACFG4_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + ldr r0, ACFG5 + ldr r1, ACFG5_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + /*--------------------------------------* + * VTP manual Calibration * + *--------------------------------------*/ + ldr r0, VTPIOCR + ldr r1, VTP_MMR0 + str r1, [r0] + + ldr r0, VTPIOCR + ldr r1, VTP_MMR1 + str r1, [r0] + + /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ + ldr r10, VTP_LOCK_COUNT +VTPLock: + subs r10, r10, $1 + bne VTPLock + + ldr r6, DFT_ENABLE + mov r10, $0x01 + str r10, [r6] + + ldr r6, DDRVTPR + ldr r7, [r6] + and r7, r7, $0x1f + and r8, r7, $0x3e0 + orr r8, r7, r8 + ldr r7, VTP_RECAL + orr r8, r7, r8 + ldr r7, VTP_EN + orr r8, r7, r8 + str r8, [r0] + + + /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ + ldr r10, VTP_LOCK_COUNT +VTP1Lock: + subs r10, r10, $1 + bne VTP1Lock + + ldr r1, [r0] + ldr r2, VTP_MASK + and r2, r1, r2 + str r2, [r0] + + ldr r6, DFT_ENABLE + mov r10, $0 + str r10, [r6] + + /* + * Call board-specific lowlevel init. + * That MUST be present and THAT returns + * back to arch calling code with "mov pc, lr." + */ + b dv_board_init + +.ltorg + +_PINMUX0: + .word 0x01c40000 /* Device Configuration Registers */ +_PINMUX1: + .word 0x01c40004 /* Device Configuration Registers */ + +_DEV_SETTING: + .word 0x00000c1f + +WAITCFG: + .word 0x01e00004 +WAITCFG_VAL: + .word 0 +ACFG3: + .word 0x01e00014 +ACFG3_VAL: + .word 0x3ffffffd +ACFG4: + .word 0x01e00018 +ACFG4_VAL: + .word 0x3ffffffd +ACFG5: + .word 0x01e0001c +ACFG5_VAL: + .word 0x3ffffffd + +MDCTL_DDR2: + .word 0x01c41a34 +MDSTAT_DDR2: + .word 0x01c41834 + +PTCMD: + .word 0x01c41120 +PTSTAT: + .word 0x01c41128 + +EINT_ENABLE0: + .word 0x01c48018 +EINT_ENABLE1: + .word 0x01c4801c + +PSC_FLAG_CLEAR: + .word 0xffffffe0 +PSC_GEM_FLAG_CLEAR: + .word 0xfffffeff + +/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ +DDRCTL: + .word 0x200000e4 +DDRCTL_VAL: + .word 0x50006405 +SDREF: + .word 0x2000000c +SDREF_VAL: + .word 0x000005c3 +SDCFG: + .word 0x20000008 +SDCFG_VAL: +#ifdef DDR_4BANKS + .word 0x00178622 +#elif defined DDR_8BANKS + .word 0x00178632 +#else +#error "Unknown DDR configuration!!!" +#endif +SDTIM0: + .word 0x20000010 +SDTIM0_VAL_162MHz: + .word 0x28923211 +SDTIM1: + .word 0x20000014 +SDTIM1_VAL_162MHz: + .word 0x0016c722 +VTPIOCR: + .word 0x200000f0 /* VTP IO Control register */ +DDRVTPR: + .word 0x01c42030 /* DDR VPTR MMR */ +VTP_MMR0: + .word 0x201f +VTP_MMR1: + .word 0xa01f +DFT_ENABLE: + .word 0x01c4004c +VTP_LOCK_COUNT: + .word 0x5b0 +VTP_MASK: + .word 0xffffdfff +VTP_RECAL: + .word 0x40000 +VTP_EN: + .word 0x02000 +CFGTEST: + .word 0x80010000 +MASK_VAL: + .word 0x00000fff + +/* GEM Power Up & LPSC Control Register */ +MDCTL_GEM: + .word 0x01c41a9c +MDSTAT_GEM: + .word 0x01c4189c + +/* For WDT reset chip bug */ +P1394: + .word 0x01c41a20 + +PLL_CLKSRC_MASK: + .word 0xfffffeff /* Mask the Clock Mode bit */ +PLL_ENSRC_MASK: + .word 0xffffffdf /* Select the PLLEN source */ +PLL_BYPASS_MASK: + .word 0xfffffffe /* Put the PLL in BYPASS */ +PLL_RESET_MASK: + .word 0xfffffff7 /* Put the PLL in Reset Mode */ +PLL_PWRUP_MASK: + .word 0xfffffffd /* PLL Power up Mask Bit */ +PLL_DISABLE_ENABLE_MASK: + .word 0xffffffef /* Enable the PLL from Disable */ +PLL_LOCK_COUNT: + .word 0x2000 + +/* PLL1-SYSTEM PLL MMRs */ +PLL1_CTL: + .word 0x01c40900 +PLL1_PLLM: + .word 0x01c40910 + +/* PLL2-SYSTEM PLL MMRs */ +PLL2_CTL: + .word 0x01c40d00 +PLL2_PLLM: + .word 0x01c40d10 +PLL2_DIV1: + .word 0x01c40d18 +PLL2_DIV2: + .word 0x01c40d1c +PLL2_PLLCMD: + .word 0x01c40d38 +PLL2_PLLSTAT: + .word 0x01c40d3c +PLL2_DIV_MASK: + .word 0xffff7fff + +MMARG_BRF0: + .word 0x01c42010 /* BRF margin mode 0 (R/W)*/ +MMARG_BRF0_VAL: + .word 0x00444400 + +DDR2_START_ADDR: + .word 0x80000000 +DUMMY_VAL: + .word 0xa55aa55a diff --git a/cpu/arm926ejs/davinci/lxt972.c b/cpu/arm926ejs/davinci/lxt972.c new file mode 100644 index 0000000..6eeb6e5 --- /dev/null +++ b/cpu/arm926ejs/davinci/lxt972.c @@ -0,0 +1,142 @@ +/* + * Intel LXT971/LXT972 PHY Driver for TI DaVinci + * (TMS320DM644x) based boards. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <net.h> +#include <lxt971a.h> +#include <asm/arch/emac_defs.h> + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +int lxt972_is_phy_connected(int phy_addr) +{ + u_int16_t id1, id2; + + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1)) + return(0); + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2)) + return(0); + + if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) + return(1); + + return(0); +} + +int lxt972_get_link_speed(int phy_addr) +{ + u_int16_t stat1, tmp; + volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) + return(0); + + if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */ + return(0); + + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) + return(0); + + tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE; + + dm644x_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp); + /* Read back */ + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) + return(0); + + + /* Speed doesn't matter, there is no setting for it in EMAC... */ + if (stat1 & PHY_LXT971_STAT2_100BTX) { + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } else { + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } + + return(0); +} + + +int lxt972_init_phy(int phy_addr) +{ + int ret = 1; + + if (!lxt972_get_link_speed(phy_addr)) { + /* Try another time */ + ret = lxt972_get_link_speed(phy_addr); + } + + /* Disable PHY Interrupts */ + dm644x_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0); + + return(ret); +} + + +int lxt972_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_COMMON_CTRL_RES_AUTO; + dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp)) + return(0); + + if (!(tmp & PHY_COMMON_STAT_AN_COMP)) + return(0); + + return (lxt972_get_link_speed(phy_addr)); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c new file mode 100644 index 0000000..127be9f --- /dev/null +++ b/cpu/arm926ejs/davinci/nand.c @@ -0,0 +1,389 @@ +/* + * NAND driver for TI DaVinci based boards. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on Linux DaVinci NAND driver by TI. Original copyright follows: + */ + +/* + * + * linux/drivers/mtd/nand/nand_davinci.c + * + * NAND Flash Driver + * + * Copyright (C) 2006 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + * + * Overview: + * This is a device driver for the NAND flash device found on the + * DaVinci board which utilizes the Samsung k9k2g08 part. + * + Modifications: + ver. 1.0: Feb 2005, Vinod/Sudhakar + - + * + */ + +#include <common.h> + +#ifdef CFG_USE_NAND +#if !defined(CFG_NAND_LEGACY) + +#include <nand.h> +#include <asm/arch/nand_defs.h> +#include <asm/arch/emif_defs.h> + +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + + switch (cmd) { + case NAND_CTL_SETCLE: + IO_ADDR_W |= MASK_CLE; + break; + case NAND_CTL_SETALE: + IO_ADDR_W |= MASK_ALE; + break; + } + + this->IO_ADDR_W = (void *)IO_ADDR_W; +} + +/* Set WP on deselect, write enable on select */ +static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) +{ +#define GPIO_SET_DATA01 0x01c67018 +#define GPIO_CLR_DATA01 0x01c6701c +#define GPIO_NAND_WP (1 << 4) +#ifdef SONATA_BOARD_GPIOWP + if (chip < 0) { + REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; + } else { + REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; + } +#endif +} + +#ifdef CFG_NAND_HW_ECC +#ifdef CFG_NAND_LARGEPAGE +static struct nand_oobinfo davinci_nand_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 12, + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, + .oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} } +}; +#elif defined(CFG_NAND_SMALLPAGE) +static struct nand_oobinfo davinci_nand_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {6, 2}, {8, 8} } +}; +#else +#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#endif + +static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) +{ + emifregs emif_addr; + int dummy; + + emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + dummy = emif_addr->NANDF1ECC; + dummy = emif_addr->NANDF2ECC; + dummy = emif_addr->NANDF3ECC; + dummy = emif_addr->NANDF4ECC; + + emif_addr->NANDFCR |= (1 << 8); +} + +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) +{ + u_int32_t ecc = 0; + emifregs emif_base_addr; + + emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + if (region == 1) + ecc = emif_base_addr->NANDF1ECC; + else if (region == 2) + ecc = emif_base_addr->NANDF2ECC; + else if (region == 3) + ecc = emif_base_addr->NANDF3ECC; + else if (region == 4) + ecc = emif_base_addr->NANDF4ECC; + + return(ecc); +} + +static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + u_int32_t tmp; + int region, n; + struct nand_chip *this = mtd->priv; + + n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; + + region = 1; + while (n--) { + tmp = nand_davinci_readecc(mtd, region); + *ecc_code++ = tmp; + *ecc_code++ = tmp >> 16; + *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0); + region++; + } + return(0); +} + +static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) +{ + u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); + + ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); + ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); + ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); +} + +static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data) +{ + u_int32_t i; + u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; + u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8]; + u_int8_t ecc_bit[24]; + u_int8_t ecc_sum = 0; + u_int8_t find_bit = 0; + u_int32_t find_byte = 0; + int is_ecc_ff; + + is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff)); + + nand_davinci_gen_true_ecc(ecc_nand); + nand_davinci_gen_true_ecc(ecc_calc); + + for (i = 0; i <= 2; i++) { + *(ecc_nand + i) = ~(*(ecc_nand + i)); + *(ecc_calc + i) = ~(*(ecc_calc + i)); + } + + for (i = 0; i < 8; i++) { + tmp0_bit[i] = *ecc_nand % 2; + *ecc_nand = *ecc_nand / 2; + } + + for (i = 0; i < 8; i++) { + tmp1_bit[i] = *(ecc_nand + 1) % 2; + *(ecc_nand + 1) = *(ecc_nand + 1) / 2; + } + + for (i = 0; i < 8; i++) { + tmp2_bit[i] = *(ecc_nand + 2) % 2; + *(ecc_nand + 2) = *(ecc_nand + 2) / 2; + } + + for (i = 0; i < 8; i++) { + comp0_bit[i] = *ecc_calc % 2; + *ecc_calc = *ecc_calc / 2; + } + + for (i = 0; i < 8; i++) { + comp1_bit[i] = *(ecc_calc + 1) % 2; + *(ecc_calc + 1) = *(ecc_calc + 1) / 2; + } + + for (i = 0; i < 8; i++) { + comp2_bit[i] = *(ecc_calc + 2) % 2; + *(ecc_calc + 2) = *(ecc_calc + 2) / 2; + } + + for (i = 0; i< 6; i++) + ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; + + for (i = 0; i < 8; i++) + ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; + + for (i = 0; i < 8; i++) + ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; + + ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; + ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; + + for (i = 0; i < 24; i++) + ecc_sum += ecc_bit[i]; + + switch (ecc_sum) { + case 0: + /* Not reached because this function is not called if + ECC values are equal */ + return 0; + case 1: + /* Uncorrectable error */ + DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + return(-1); + case 12: + /* Correctable error */ + find_byte = (ecc_bit[23] << 8) + + (ecc_bit[21] << 7) + + (ecc_bit[19] << 6) + + (ecc_bit[17] << 5) + + (ecc_bit[15] << 4) + + (ecc_bit[13] << 3) + + (ecc_bit[11] << 2) + + (ecc_bit[9] << 1) + + ecc_bit[7]; + + find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; + + DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); + + page_data[find_byte] ^= (1 << find_bit); + + return(0); + default: + if (is_ecc_ff) { + if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) + return(0); + } + DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); + return(-1); + } +} + +static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + struct nand_chip *this; + int block_count = 0, i, rc; + + this = mtd->priv; + block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; + for (i = 0; i < block_count; i++) { + if (memcmp(read_ecc, calc_ecc, 3) != 0) { + rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat); + if (rc < 0) { + return(rc); + } + } + read_ecc += 3; + calc_ecc += 3; + dat += 512; + } + return(0); +} +#endif + +static int nand_davinci_dev_ready(struct mtd_info *mtd) +{ + emifregs emif_addr; + + emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + return(emif_addr->NANDFSR & 0x1); +} + +static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + while(!nand_davinci_dev_ready(mtd)) {;} + *NAND_CE0CLE = NAND_STATUS; + return(*NAND_CE0DATA); +} + +static void nand_flash_init(void) +{ + u_int32_t acfg1 = 0x3ffffffc; + u_int32_t acfg2 = 0x3ffffffc; + u_int32_t acfg3 = 0x3ffffffc; + u_int32_t acfg4 = 0x3ffffffc; + emifregs emif_regs; + + /*------------------------------------------------------------------* + * NAND FLASH CHIP TIMEOUT @ 459 MHz * + * * + * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * + * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * + * * + *------------------------------------------------------------------*/ + acfg1 = 0 + | (0 << 31 ) /* selectStrobe */ + | (0 << 30 ) /* extWait */ + | (1 << 26 ) /* writeSetup 10 ns */ + | (3 << 20 ) /* writeStrobe 40 ns */ + | (1 << 17 ) /* writeHold 10 ns */ + | (1 << 13 ) /* readSetup 10 ns */ + | (5 << 7 ) /* readStrobe 60 ns */ + | (1 << 4 ) /* readHold 10 ns */ + | (3 << 2 ) /* turnAround ?? ns */ + | (0 << 0 ) /* asyncSize 8-bit bus */ + ; + + emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + emif_regs->AWCCR |= 0x10000000; + emif_regs->AB1CR = acfg1; /* 0x08244128 */; + emif_regs->AB2CR = acfg2; + emif_regs->AB3CR = acfg3; + emif_regs->AB4CR = acfg4; + emif_regs->NANDFCR = 0x00000101; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; + nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; + nand->chip_delay = 0; + nand->select_chip = nand_davinci_select_chip; +#ifdef CFG_NAND_USE_FLASH_BBT + nand->options = NAND_USE_FLASH_BBT; +#endif +#ifdef CFG_NAND_HW_ECC +#ifdef CFG_NAND_LARGEPAGE + nand->eccmode = NAND_ECC_HW12_2048; +#elif defined(CFG_NAND_SMALLPAGE) + nand->eccmode = NAND_ECC_HW3_512; +#else +#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#endif + nand->autooob = &davinci_nand_oobinfo; + nand->calculate_ecc = nand_davinci_calculate_ecc; + nand->correct_data = nand_davinci_correct_data; + nand->enable_hwecc = nand_davinci_enable_hwecc; +#else + nand->eccmode = NAND_ECC_SOFT; +#endif + + /* Set address of hardware control function */ + nand->hwcontrol = nand_davinci_hwcontrol; + + nand->dev_ready = nand_davinci_dev_ready; + nand->waitfunc = nand_davinci_waitfunc; + + nand_flash_init(); + + return(0); +} + +#else +#error "U-Boot legacy NAND support not available for DaVinci chips" +#endif +#endif /* CFG_USE_NAND */ diff --git a/cpu/arm926ejs/davinci/reset.S b/cpu/arm926ejs/davinci/reset.S new file mode 100644 index 0000000..a687d44 --- /dev/null +++ b/cpu/arm926ejs/davinci/reset.S @@ -0,0 +1,77 @@ +/* + * Processor reset using WDT for TI TMS320DM644x SoC. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + ldr r0, WDT_TGCR + mov r1, $0x08 + str r1, [r0] + ldr r1, [r0] + orr r1, r1, $0x03 + str r1, [r0] + mov r1, $0 + ldr r0, WDT_TIM12 + str r1, [r0] + ldr r0, WDT_TIM34 + str r1, [r0] + ldr r0, WDT_PRD12 + str r1, [r0] + ldr r0, WDT_PRD34 + str r1, [r0] + ldr r0, WDT_TCR + ldr r1, [r0] + orr r1, r1, $0x40 + str r1, [r0] + ldr r0, WDT_WDTCR + ldr r1, [r0] + orr r1, r1, $0x4000 + str r1, [r0] + ldr r1, WDTCR_VAL1 + str r1, [r0] + ldr r1, WDTCR_VAL2 + str r1, [r0] + nop + nop + nop + nop +reset_cpu_loop: + b reset_cpu_loop + +WDT_TGCR: + .word 0x01c21c24 +WDT_TIM12: + .word 0x01c21c10 +WDT_TIM34: + .word 0x01c21c14 +WDT_PRD12: + .word 0x01c21c18 +WDT_PRD34: + .word 0x01c21c1c +WDT_TCR: + .word 0x01c21c20 +WDT_WDTCR: + .word 0x01c21c28 +WDTCR_VAL1: + .word 0xa5c64000 +WDTCR_VAL2: + .word 0xda7e4000 diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c new file mode 100644 index 0000000..c6b1dda --- /dev/null +++ b/cpu/arm926ejs/davinci/timer.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arm926ejs.h> + +typedef volatile struct { + u_int32_t pid12; + u_int32_t emumgt_clksped; + u_int32_t gpint_en; + u_int32_t gpdir_dat; + u_int32_t tim12; + u_int32_t tim34; + u_int32_t prd12; + u_int32_t prd34; + u_int32_t tcr; + u_int32_t tgcr; + u_int32_t wdtcr; + u_int32_t tlgc; + u_int32_t tlmr; +} davinci_timer; + +davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; + +#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) +#define READ_TIMER timer->tim34 + +static ulong timestamp; +static ulong lastinc; + +int timer_init(void) +{ + /* We are using timer34 in unchained 32-bit mode, full speed */ + timer->tcr = 0x0; + timer->tgcr = 0x0; + timer->tgcr = 0x06; + timer->tim34 = 0x0; + timer->prd34 = TIMER_LOAD_VAL; + lastinc = 0; + timer->tcr = 0x80 << 16; + timestamp = 0; + + return(0); +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return(get_timer_masked() - base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +void reset_timer_masked(void) +{ + lastinc = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_raw(void) +{ + ulong now = READ_TIMER; + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + return timestamp; +} + +ulong get_timer_masked(void) +{ + return(get_timer_raw() / TIMER_LOAD_VAL); +} + +void udelay_masked(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + tmo = CFG_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= 1000; + + endtime = get_timer_raw() + tmo; + + do { + ulong now = get_timer_raw(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return(get_timer(0)); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return(tbclk); +} diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index 3be565a..accae6e 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -42,7 +42,7 @@ int checkcpu (void) u32 spridr = immr->sysconf.spridr; char buf[32]; - puts("CPU: "); + puts ("CPU: "); switch (spridr & 0xffff0000) { case SPR_5121E: diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index 1c87a53..3c142a9 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -17,10 +17,10 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUG 0 -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC512x_FEC) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -626,7 +626,7 @@ int mpc512x_fec_initialize (bd_t * bis) sprintf (dev->name, "FEC ETHERNET"); eth_register (dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, fec512x_miiphy_read, fec512x_miiphy_write); #endif diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c index 40281a2..8455c92 100644 --- a/cpu/mpc512x/traps.c +++ b/cpu/mpc512x/traps.c @@ -106,7 +106,7 @@ MachineCheckException (struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -144,7 +144,7 @@ MachineCheckException (struct pt_regs *regs) void AlignmentException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -156,7 +156,7 @@ AlignmentException (struct pt_regs *regs) void ProgramCheckException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -168,7 +168,7 @@ ProgramCheckException (struct pt_regs *regs) void SoftEmuException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -181,7 +181,7 @@ SoftEmuException (struct pt_regs *regs) void UnknownException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -190,7 +190,7 @@ UnknownException (struct pt_regs *regs) _exception (0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#ifdef CONFIG_CMD_BEDBUG extern void do_bedbug_breakpoint (struct pt_regs *); #endif @@ -199,7 +199,7 @@ DebugException (struct pt_regs *regs) { printf ("Debugger trap at @ %lx\n", regs->nip ); show_regs (regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#ifdef CONFIG_CMD_BEDBUG do_bedbug_breakpoint (regs); #endif } diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 2c17cee..54f0c83 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -576,7 +576,7 @@ long int spd_sdram() if (spd.dataw_lsb == 0x20) { if (spd.mem_type == SPD_MEMTYPE_DDR) burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) + else burstlen = 0x02; /* 32 bit data bus, burst len is 4 */ printf("\n DDR DIMM: data bus width is 32 bit"); } else { diff --git a/cpu/nios/cpu.c b/cpu/nios/cpu.c index d2bb2c0..5519e82 100644 --- a/cpu/nios/cpu.c +++ b/cpu/nios/cpu.c @@ -34,7 +34,7 @@ int checkcpu (void) /* Get cpu version info */ val = rdctl (CTL_CPU_ID); - printf ("CPU: "); + puts ("CPU: "); printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 "); rev_major = (val>>12) & 0x07; rev_minor = (val>>4) & 0x0ff; diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index 88c1df6..aee8727 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -37,6 +37,7 @@ #include <command.h> #include <watchdog.h> #include <malloc.h> +#include <div64.h> #include <nand.h> #include <jffs2/jffs2.h> @@ -208,10 +209,10 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) } if (!opts->quiet) { - int percent = (int) - ((unsigned long long) + unsigned long long n =(unsigned long long) (erase.addr+meminfo->erasesize-opts->offset) - * 100 / erase_length); + * 100; + int percent = (int)do_div(n, erase_length); /* output progress message only at whole percent * steps to reduce the number of messages printed @@ -475,10 +476,9 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) imglen -= readlen; if (!opts->quiet) { - int percent = (int) - ((unsigned long long) - (opts->length-imglen) * 100 - / opts->length); + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; + int percent = (int)do_div(n, opts->length); /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles @@ -651,10 +651,9 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) } if (!opts->quiet) { - int percent = (int) - ((unsigned long long) - (opts->length-imglen) * 100 - / opts->length); + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; + int percent = (int)do_div(n ,opts->length); /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles diff --git a/include/_exports.h b/include/_exports.h index da6e088..af43885 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -14,6 +14,9 @@ EXPORT_FUNC(vprintf) EXPORT_FUNC(do_reset) EXPORT_FUNC(getenv) EXPORT_FUNC(setenv) +#ifdef CONFIG_HAS_UID +EXPORT_FUNC(forceenv) +#endif EXPORT_FUNC(simple_strtoul) EXPORT_FUNC(simple_strtol) EXPORT_FUNC(strcmp) diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h new file mode 100644 index 0000000..0e10116 --- /dev/null +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -0,0 +1,311 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _DM644X_EMAC_H_ +#define _DM644X_EMAC_H_ + +#include <asm/arch/hardware.h> + +#define EMAC_BASE_ADDR (0x01c80000) +#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) +#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) +#define EMAC_MDIO_BASE_ADDR (0x01c84000) + +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ + +/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ + +/* Number of RX packet buffers + * NOTE: Only 1 buffer supported as of now + */ +#define EMAC_MAX_RX_BUFFERS 10 + + +/*********************************************** + ******** Internally used macros *************** + ***********************************************/ + +#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0 + +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and + * reserve space for 64 descriptors max + */ +#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000 + +/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc + +/* MII Status Register */ +#define MII_STATUS_REG 1 + +/* Number of statistics registers */ +#define EMAC_NUM_STATS 36 + + +/* EMAC Descriptor */ +typedef volatile struct _emac_desc +{ + u_int32_t next; /* Pointer to next descriptor in chain */ + u_int8_t *buffer; /* Pointer to data buffer */ + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ +} emac_desc; + +/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) + +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) + +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) + +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) + + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +/* Ethernet MAC Registers Structure */ +typedef struct { + dv_reg TXIDVER; + dv_reg TXCONTROL; + dv_reg TXTEARDOWN; + u_int8_t RSVD0[4]; + dv_reg RXIDVER; + dv_reg RXCONTROL; + dv_reg RXTEARDOWN; + u_int8_t RSVD1[100]; + dv_reg TXINTSTATRAW; + dv_reg TXINTSTATMASKED; + dv_reg TXINTMASKSET; + dv_reg TXINTMASKCLEAR; + dv_reg MACINVECTOR; + u_int8_t RSVD2[12]; + dv_reg RXINTSTATRAW; + dv_reg RXINTSTATMASKED; + dv_reg RXINTMASKSET; + dv_reg RXINTMASKCLEAR; + dv_reg MACINTSTATRAW; + dv_reg MACINTSTATMASKED; + dv_reg MACINTMASKSET; + dv_reg MACINTMASKCLEAR; + u_int8_t RSVD3[64]; + dv_reg RXMBPENABLE; + dv_reg RXUNICASTSET; + dv_reg RXUNICASTCLEAR; + dv_reg RXMAXLEN; + dv_reg RXBUFFEROFFSET; + dv_reg RXFILTERLOWTHRESH; + u_int8_t RSVD4[8]; + dv_reg RX0FLOWTHRESH; + dv_reg RX1FLOWTHRESH; + dv_reg RX2FLOWTHRESH; + dv_reg RX3FLOWTHRESH; + dv_reg RX4FLOWTHRESH; + dv_reg RX5FLOWTHRESH; + dv_reg RX6FLOWTHRESH; + dv_reg RX7FLOWTHRESH; + dv_reg RX0FREEBUFFER; + dv_reg RX1FREEBUFFER; + dv_reg RX2FREEBUFFER; + dv_reg RX3FREEBUFFER; + dv_reg RX4FREEBUFFER; + dv_reg RX5FREEBUFFER; + dv_reg RX6FREEBUFFER; + dv_reg RX7FREEBUFFER; + dv_reg MACCONTROL; + dv_reg MACSTATUS; + dv_reg EMCONTROL; + dv_reg FIFOCONTROL; + dv_reg MACCONFIG; + dv_reg SOFTRESET; + u_int8_t RSVD5[88]; + dv_reg MACSRCADDRLO; + dv_reg MACSRCADDRHI; + dv_reg MACHASH1; + dv_reg MACHASH2; + dv_reg BOFFTEST; + dv_reg TPACETEST; + dv_reg RXPAUSE; + dv_reg TXPAUSE; + u_int8_t RSVD6[16]; + dv_reg RXGOODFRAMES; + dv_reg RXBCASTFRAMES; + dv_reg RXMCASTFRAMES; + dv_reg RXPAUSEFRAMES; + dv_reg RXCRCERRORS; + dv_reg RXALIGNCODEERRORS; + dv_reg RXOVERSIZED; + dv_reg RXJABBER; + dv_reg RXUNDERSIZED; + dv_reg RXFRAGMENTS; + dv_reg RXFILTERED; + dv_reg RXQOSFILTERED; + dv_reg RXOCTETS; + dv_reg TXGOODFRAMES; + dv_reg TXBCASTFRAMES; + dv_reg TXMCASTFRAMES; + dv_reg TXPAUSEFRAMES; + dv_reg TXDEFERRED; + dv_reg TXCOLLISION; + dv_reg TXSINGLECOLL; + dv_reg TXMULTICOLL; + dv_reg TXEXCESSIVECOLL; + dv_reg TXLATECOLL; + dv_reg TXUNDERRUN; + dv_reg TXCARRIERSENSE; + dv_reg TXOCTETS; + dv_reg FRAME64; + dv_reg FRAME65T127; + dv_reg FRAME128T255; + dv_reg FRAME256T511; + dv_reg FRAME512T1023; + dv_reg FRAME1024TUP; + dv_reg NETOCTETS; + dv_reg RXSOFOVERRUNS; + dv_reg RXMOFOVERRUNS; + dv_reg RXDMAOVERRUNS; + u_int8_t RSVD7[624]; + dv_reg MACADDRLO; + dv_reg MACADDRHI; + dv_reg MACINDEX; + u_int8_t RSVD8[244]; + dv_reg TX0HDP; + dv_reg TX1HDP; + dv_reg TX2HDP; + dv_reg TX3HDP; + dv_reg TX4HDP; + dv_reg TX5HDP; + dv_reg TX6HDP; + dv_reg TX7HDP; + dv_reg RX0HDP; + dv_reg RX1HDP; + dv_reg RX2HDP; + dv_reg RX3HDP; + dv_reg RX4HDP; + dv_reg RX5HDP; + dv_reg RX6HDP; + dv_reg RX7HDP; + dv_reg TX0CP; + dv_reg TX1CP; + dv_reg TX2CP; + dv_reg TX3CP; + dv_reg TX4CP; + dv_reg TX5CP; + dv_reg TX6CP; + dv_reg TX7CP; + dv_reg RX0CP; + dv_reg RX1CP; + dv_reg RX2CP; + dv_reg RX3CP; + dv_reg RX4CP; + dv_reg RX5CP; + dv_reg RX6CP; + dv_reg RX7CP; +} emac_regs; + +/* EMAC Wrapper Registers Structure */ +typedef struct { + u_int8_t RSVD0[4100]; + dv_reg EWCTL; + dv_reg EWINTTCNT; +} ewrap_regs; + + +/* EMAC MDIO Registers Structure */ +typedef struct { + dv_reg VERSION; + dv_reg CONTROL; + dv_reg ALIVE; + dv_reg LINK; + dv_reg LINKINTRAW; + dv_reg LINKINTMASKED; + u_int8_t RSVD0[8]; + dv_reg USERINTRAW; + dv_reg USERINTMASKED; + dv_reg USERINTMASKSET; + dv_reg USERINTMASKCLEAR; + u_int8_t RSVD1[80]; + dv_reg USERACCESS0; + dv_reg USERPHYSEL0; + dv_reg USERACCESS1; + dv_reg USERPHYSEL1; +} mdio_regs; + +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); + +typedef struct +{ + char name[64]; + int (*init)(int phy_addr); + int (*is_phy_connected)(int phy_addr); + int (*get_link_speed)(int phy_addr); + int (*auto_negotiate)(int phy_addr); +} phy_t; + +#define PHY_LXT972 (0x001378e2) +int lxt972_is_phy_connected(int phy_addr); +int lxt972_get_link_speed(int phy_addr); +int lxt972_init_phy(int phy_addr); +int lxt972_auto_negotiate(int phy_addr); + +#define PHY_DP83848 (0x20005c90) +int dp83848_is_phy_connected(int phy_addr); +int dp83848_get_link_speed(int phy_addr); +int dp83848_init_phy(int phy_addr); +int dp83848_auto_negotiate(int phy_addr); + +#endif /* _DM644X_EMAC_H_ */ diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h new file mode 100644 index 0000000..646fc77 --- /dev/null +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include <asm/arch/hardware.h> + +typedef struct { + dv_reg ERCSR; + dv_reg AWCCR; + dv_reg SDBCR; + dv_reg SDRCR; + dv_reg AB1CR; + dv_reg AB2CR; + dv_reg AB3CR; + dv_reg AB4CR; + dv_reg SDTIMR; + dv_reg DDRSR; + dv_reg DDRPHYCR; + dv_reg DDRPHYSR; + dv_reg TOTAR; + dv_reg TOTACTR; + dv_reg DDRPHYID_REV; + dv_reg SDSRETR; + dv_reg EIRR; + dv_reg EIMR; + dv_reg EIMSR; + dv_reg EIMCR; + dv_reg IOCTRLR; + dv_reg IOSTATR; + u_int8_t RSVD0[8]; + dv_reg NANDFCR; + dv_reg NANDFSR; + u_int8_t RSVD1[8]; + dv_reg NANDF1ECC; + dv_reg NANDF2ECC; + dv_reg NANDF3ECC; + dv_reg NANDF4ECC; +} emif_registers; + +typedef emif_registers *emifregs; +#endif diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 0000000..ebcdcfe --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <config.h> +#include <asm/sizes.h> + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int * dv_reg_p; + +/* + * Base register addresses + */ +#define DAVINCI_DMA_3PCC_BASE (0x01c00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) +#define DAVINCI_UART0_BASE (0x01c20000) +#define DAVINCI_UART1_BASE (0x01c20400) +#define DAVINCI_UART2_BASE (0x01c20800) +#define DAVINCI_I2C_BASE (0x01c21000) +#define DAVINCI_TIMER0_BASE (0x01c21400) +#define DAVINCI_TIMER1_BASE (0x01c21800) +#define DAVINCI_WDOG_BASE (0x01c21c00) +#define DAVINCI_PWM0_BASE (0x01c22000) +#define DAVINCI_PWM1_BASE (0x01c22400) +#define DAVINCI_PWM2_BASE (0x01c22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000) +#define DAVINCI_ARM_INTC_BASE (0x01c48000) +#define DAVINCI_IEEE1394_BASE (0x01c60000) +#define DAVINCI_USB_OTG_BASE (0x01c64000) +#define DAVINCI_CFC_ATA_BASE (0x01c66000) +#define DAVINCI_SPI_BASE (0x01c66800) +#define DAVINCI_GPIO_BASE (0x01c67000) +#define DAVINCI_UHPI_BASE (0x01c67800) +#define DAVINCI_VPSS_REGS_BASE (0x01c70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000) +#define DAVINCI_IMCOP_BASE (0x01cc0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000) +#define DAVINCI_VLYNQ_BASE (0x01e01000) +#define DAVINCI_MCBSP_BASE (0x01e02000) +#define DAVINCI_MMC_SD_BASE (0x01e10000) +#define DAVINCI_MS_BASE (0x01e20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000) + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +/* Some PSC defines */ +#define PSC_CHP_SHRTSW (0x01c40038) +#define PSC_GBLCTL (0x01c41010) +#define PSC_EPCPR (0x01c41070) +#define PSC_EPCCR (0x01c41078) +#define PSC_PTCMD (0x01c41120) +#define PSC_PTSTAT (0x01c41128) +#define PSC_PDSTAT (0x01c41200) +#define PSC_PDSTAT1 (0x01c41204) +#define PSC_PDCTL (0x01c41300) +#define PSC_PDCTL1 (0x01c41304) + +#define PSC_MDCTL_BASE (0x01c41a00) +#define PSC_MDSTAT_BASE (0x01c41800) + +#define VDD3P3V_PWDN (0x01c40048) +#define UART0_PWREMU_MGMT (0x01c20030) + +#define PSC_SILVER_BULLET (0x01c41a20) + +/* Some PLL defines */ +#define PLL1_PLLM (0x01c40910) +#define PLL2_PLLM (0x01c40d10) +#define PLL2_DIV2 (0x01c40d1c) + +/* Miscellania... */ +#define VBPR (0x20000020) +#define PINMUX0 (0x01c40000) +#define PINMUX1 (0x01c40004) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h new file mode 100644 index 0000000..2e902e1 --- /dev/null +++ b/include/asm-arm/arch-davinci/i2c_defs.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * + * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DAVINCI_I2C_H_ +#define _DAVINCI_I2C_H_ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_BASE 0x01c21000 + +#define I2C_OA (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_SCLL (I2C_BASE + 0x0c) +#define I2C_SCLH (I2C_BASE + 0x10) +#define I2C_CNT (I2C_BASE + 0x14) +#define I2C_DRR (I2C_BASE + 0x18) +#define I2C_SA (I2C_BASE + 0x1c) +#define I2C_DXR (I2C_BASE + 0x20) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_IV (I2C_BASE + 0x28) +#define I2C_PSC (I2C_BASE + 0x30) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ +#define I2C_INTCODE_SCD 6 /* Stop condition detect */ + + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 5) /* I2C module enable */ +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ + +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ + +#endif diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h new file mode 100644 index 0000000..619bd47 --- /dev/null +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Parts shamelesly stolen from Linux Kernel source tree. + * + * ------------------------------------------------------------ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NAND_DEFS_H_ +#define _NAND_DEFS_H_ + +#include <asm/arch/hardware.h> + +#define MASK_CLE 0x10 +#define MASK_ALE 0x0a + +#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10)) +#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a)) +#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE) + +typedef struct { + u_int32_t NRCSR; + u_int32_t AWCCR; + u_int8_t RSVD0[8]; + u_int32_t AB1CR; + u_int32_t AB2CR; + u_int32_t AB3CR; + u_int32_t AB4CR; + u_int8_t RSVD1[32]; + u_int32_t NIRR; + u_int32_t NIMR; + u_int32_t NIMSR; + u_int32_t NIMCR; + u_int8_t RSVD2[16]; + u_int32_t NANDFCR; + u_int32_t NANDFSR; + u_int8_t RSVD3[8]; + u_int32_t NANDF1ECC; + u_int32_t NANDF2ECC; + u_int32_t NANDF3ECC; + u_int32_t NANDF4ECC; + u_int8_t RSVD4[4]; + u_int32_t IODFTECR; + u_int32_t IODFTGCR; + u_int8_t RSVD5[4]; + u_int32_t IODFTMRLR; + u_int32_t IODFTMRMR; + u_int32_t IODFTMRMSBR; + u_int8_t RSVD6[20]; + u_int32_t MODRNR; + u_int8_t RSVD7[76]; + u_int32_t CE0DATA; + u_int32_t CE0ALE; + u_int32_t CE0CLE; + u_int8_t RSVD8[4]; + u_int32_t CE1DATA; + u_int32_t CE1ALE; + u_int32_t CE1CLE; + u_int8_t RSVD9[4]; + u_int32_t CE2DATA; + u_int32_t CE2ALE; + u_int32_t CE2CLE; + u_int8_t RSVD10[4]; + u_int32_t CE3DATA; + u_int32_t CE3ALE; + u_int32_t CE3CLE; +} nand_registers; + +typedef volatile nand_registers *nandregs; + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#ifdef CFG_NAND_HW_ECC +#define NAND_Ecc_P1e (1 << 0) +#define NAND_Ecc_P2e (1 << 1) +#define NAND_Ecc_P4e (1 << 2) +#define NAND_Ecc_P8e (1 << 3) +#define NAND_Ecc_P16e (1 << 4) +#define NAND_Ecc_P32e (1 << 5) +#define NAND_Ecc_P64e (1 << 6) +#define NAND_Ecc_P128e (1 << 7) +#define NAND_Ecc_P256e (1 << 8) +#define NAND_Ecc_P512e (1 << 9) +#define NAND_Ecc_P1024e (1 << 10) +#define NAND_Ecc_P2048e (1 << 11) + +#define NAND_Ecc_P1o (1 << 16) +#define NAND_Ecc_P2o (1 << 17) +#define NAND_Ecc_P4o (1 << 18) +#define NAND_Ecc_P8o (1 << 19) +#define NAND_Ecc_P16o (1 << 20) +#define NAND_Ecc_P32o (1 << 21) +#define NAND_Ecc_P64o (1 << 22) +#define NAND_Ecc_P128o (1 << 23) +#define NAND_Ecc_P256o (1 << 24) +#define NAND_Ecc_P512o (1 << 25) +#define NAND_Ecc_P1024o (1 << 26) +#define NAND_Ecc_P2048o (1 << 27) + +#define TF(v) (v ? 1 : 0) + +#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) +#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) +#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) +#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) +#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) +#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) +#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) +#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) + +#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) +#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) +#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) +#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) +#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) +#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) +#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) +#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) + +#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) +#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) +#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) +#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) +#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) +#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) +#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) +#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) + +#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) +#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) +#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) +#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) +#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) +#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) +#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) +#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) + +#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) +#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) +#endif + +#endif diff --git a/include/common.h b/include/common.h index a822d28..27a660a 100644 --- a/include/common.h +++ b/include/common.h @@ -241,6 +241,9 @@ int saveenv (void); void inline setenv (char *, char *); #else void setenv (char *, char *); +#ifdef CONFIG_HAS_UID +void forceenv (char *, char *); +#endif #endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include <asm/mach-types.h> diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 1a7167b..53261548 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -85,7 +85,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE #define CFG_OHCI_BE_CONTROLLER #undef CFG_USB_OHCI_BOARD_INIT diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 8360d8c..3d98500 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -131,8 +131,9 @@ /* USB */ #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define CONFIG_USB_OHCI_NEW -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB #undef CFG_USB_OHCI_BOARD_INIT #define CFG_USB_OHCI_CPU_INIT @@ -140,8 +141,6 @@ #define CFG_USB_OHCI_SLOT_NAME "mpc5200" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 -#else -#define ADD_USB_CMD 0 #endif #ifndef CONFIG_CAM5200 diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 89564a9..22eac1b 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -241,7 +241,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 0x1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_ETHADDR 00:e0:5e:00:e5:14 #if 0 /* @@ -267,22 +266,20 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_MII \ - | CFG_CMD_I2C) +#define CONFIG_CMD_PCI #endif -#include <cmd_confdefs.h> - /* * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set @@ -299,7 +296,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -321,7 +318,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -337,7 +334,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -348,18 +345,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HOSTNAME ads5121 -#define CONFIG_ROOTPATH /nfsroot/rootfs #define CONFIG_BOOTFILE uImage -#define CONFIG_IPADDR 192.168.160.77 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.0.0 - #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ -//#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 @@ -383,9 +373,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ - "update=protect off fff00000 fff3ffff; " \ - "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "load=tftp 200000 /tftpboot/ads5121/u-boot.bin\0" \ + "update=protect off FFF00000 +${filesize};" \ + "era FFF00000 +${filesize};cp.b 200000 FFF00000 ${filesize}\0" \ "upd=run load;run update\0" \ "" diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 7662856..56c0ecb 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -35,27 +35,22 @@ /* * Supported commands */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_I2C | \ - CFG_CMD_FLASH | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP | \ - CFG_CMD_USB | \ - CFG_CMD_FAT | \ - CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB /* * Serial console configuration @@ -344,7 +339,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h new file mode 100644 index 0000000..8ecd059 --- /dev/null +++ b/include/configs/davinci_dvevm.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * Define this to make U-Boot skip low level initialization when loaded + * by initial bootloader. Not required by NAND U-Boot version but IS + * required for a NOR version used to burn the real NOR U-Boot into + * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive + * so it is NOT possible to build a U-Boot with both NAND and NOR routines. + * NOR U-Boot is loaded directly from Flash so it must perform all the + * low level initialization itself. NAND version is loaded by an initial + * bootloader (UBL in TI-ese) that performs such an initialization so it's + * skipped in NAND version. The third DaVinci boot mode loads a bootloader + * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) + * performing low level init prior to loading. All that means we can NOT use + * NAND version to put U-Boot into NOR because it doesn't have NOR support and + * we can NOT use NOR version because it performs low level initialization + * effectively destroying itself in DDR memory. That's why a separate NOR + * version with this define is needed. It is loaded via UART, then one uses + * it to somehow download a proper NOR version built WITHOUT this define to + * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze + * NOR support into the initial bootloader so it won't be needed but DaVinci + * static RAM might be too small for this (I have something like 2Kbytes left + * as of now, without NOR support) so this might've not happened... + * +#define CONFIG_NOR_UART_BOOT + */ + +/*=======*/ +/* Board */ +/*=======*/ +#define DV_EVM +#define CFG_NAND_SMALLPAGE +#define CFG_USE_NOR +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*====================================================*/ +/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ +/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ +/*====================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ +#define DDR_8BANKS /* 8-bank DDR2 (256MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CFG_USE_NAND +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#ifdef CFG_NAND_SMALLPAGE +#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_16K +#else +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define DEF_BOOTM "" +#elif defined(CFG_USE_NOR) +#ifdef CONFIG_NOR_UART_BOOT +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#else +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#endif +#define CFG_ENV_IS_IN_FLASH +#undef CFG_NO_FLASH +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ +#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3) +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ +#endif +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#ifdef CFG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#elif defined(CFG_USE_NOR) +#define CONFIG_CMD_JFFS2 +#else +#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" +#endif +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h new file mode 100644 index 0000000..96c9a30 --- /dev/null +++ b/include/configs/davinci_schmoogie.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/*=======*/ +/* Board */ +/*=======*/ +#define SCHMOOGIE +#define CFG_NAND_LARGEPAGE +#define CFG_USE_NAND +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +/*=====================*/ +/* Board related stuff */ +/*=====================*/ +#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ +#define CFG_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ +#define CONFIG_HAS_UID +#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ +#define CFG_UID_ADDR 0x50 /* UID chip I2C address */ +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NAND +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h new file mode 100644 index 0000000..de8c4fa --- /dev/null +++ b/include/configs/davinci_sonata.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * Define this to make U-Boot skip low level initialization when loaded + * by initial bootloader. Not required by NAND U-Boot version but IS + * required for a NOR version used to burn the real NOR U-Boot into + * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive + * so it is NOT possible to build a U-Boot with both NAND and NOR routines. + * NOR U-Boot is loaded directly from Flash so it must perform all the + * low level initialization itself. NAND version is loaded by an initial + * bootloader (UBL in TI-ese) that performs such an initialization so it's + * skipped in NAND version. The third DaVinci boot mode loads a bootloader + * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) + * performing low level init prior to loading. All that means we can NOT use + * NAND version to put U-Boot into NOR because it doesn't have NOR support and + * we can NOT use NOR version because it performs low level initialization + * effectively destroying itself in DDR memory. That's why a separate NOR + * version with this define is needed. It is loaded via UART, then one uses + * it to somehow download a proper NOR version built WITHOUT this define to + * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze + * NOR support into the initial bootloader so it won't be needed but DaVinci + * static RAM might be too small for this (I have something like 2Kbytes left + * as of now, without NOR support) so this might've not happened... + * +#define CONFIG_NOR_UART_BOOT + */ + +/*=======*/ +/* Board */ +/*=======*/ +#define SONATA_BOARD +#define CFG_NAND_SMALLPAGE +#define CFG_USE_NOR +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*====================================================*/ +/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ +/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ +/*====================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CFG_USE_NAND +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_16K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define DEF_BOOTM "" +#elif defined(CFG_USE_NOR) +#ifdef CONFIG_NOR_UART_BOOT +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#else +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#endif +#define CFG_ENV_IS_IN_FLASH +#undef CFG_NO_FLASH +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ +#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2) +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ +#endif +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#ifdef CFG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#elif defined(CFG_USE_NOR) +#define CONFIG_CMD_JFFS2 +#else +#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" +#endif +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 744f551..cc2dbcd 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -111,11 +111,13 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB +#undef CONFIG_CMD_NET + /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -131,20 +133,30 @@ # define CFG__LINUX_CONSOLE "ttyS0" #else # define CFG__BOARDNAME "mcc200" -# define CFG__LINUX_CONSOLE "ttyEU7" +# define CFG__LINUX_CONSOLE "ttyEU5" #endif +/* Network */ +#define CONFIG_ETHADDR 00:17:17:ff:00:00 +#define CONFIG_IPADDR 10.76.9.29 +#define CONFIG_SERVERIP 10.76.9.1 + +#include <version.h> /* For U-Boot version */ + #define CONFIG_EXTRA_ENV_SETTINGS \ + "ubootver=" U_BOOT_VERSION "\0" \ "netdev=eth0\0" \ "hostname=" CFG__BOARDNAME "\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "ramargs=setenv bootargs root=/dev/mtdblock2 " \ + "rootfstype=cramfs\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ + "console=${console},${baudrate} " \ + "ubootver=${ubootver} board=${board}\0" \ "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addcons;" \ @@ -156,6 +168,7 @@ "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ "text_base=" MK_STR(TEXT_BASE) "\0" \ + "kernel_addr=0xFC0C0000\0" \ "update=protect off ${text_base} +${filesize};" \ "era ${text_base} +${filesize};" \ "cp.b 200000 ${text_base} ${filesize}\0" \ @@ -256,7 +269,7 @@ /* * Ethernet configuration */ -#define CONFIG_MPC5xxx_FEC 1 +/*#define CONFIG_MPC5xxx_FEC 1*/ /* * Define CONFIG_FEC_10MBIT to force FEC at 10Mb */ @@ -337,6 +350,13 @@ #define CFG_CS1_SIZE 0x00001000 #define CFG_CS1_CFG 0x1d300 +/* Leica - build revision resistors */ +/* +#define CFG_CS3_START 0x80020000 +#define CFG_CS3_SIZE 0x00000004 +#define CFG_CS3_CFG 0x1d300 +*/ + /* * Select one of quarts as a default * console. If undefined - PSC console @@ -392,4 +412,8 @@ #define CONFIG_USB_CLOCK 0x0001BBBB #define CONFIG_USB_CONFIG 0x00005000 +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR "432" +#define CONFIG_SILENT_CONSOLE 1 + #endif /* __CONFIG_H */ diff --git a/include/asm-avr32/div64.h b/include/div64.h index 2e0ba83..2e0ba83 100644 --- a/include/asm-avr32/div64.h +++ b/include/div64.h diff --git a/include/dp83848.h b/include/dp83848.h new file mode 100644 index 0000000..274bc4c --- /dev/null +++ b/include/dp83848.h @@ -0,0 +1,88 @@ +/* + * DP83848 ethernet Physical layer + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + + +/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ + +#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ +#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ +#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ +#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ +#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ +#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ +#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ +#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ +#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ +#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ + +/*--Bit definitions: DP83848_CTL_REG */ +#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ +#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ +#define DP83848_SPEED_SELECT (1 << 13) +#define DP83848_AUTONEG (1 << 12) +#define DP83848_POWER_DOWN (1 << 11) +#define DP83848_ISOLATE (1 << 10) +#define DP83848_RESTART_AUTONEG (1 << 9) +#define DP83848_DUPLEX_MODE (1 << 8) +#define DP83848_COLLISION_TEST (1 << 7) + +/*--Bit definitions: DP83848_STAT_REG */ +#define DP83848_100BASE_T4 (1 << 15) +#define DP83848_100BASE_TX_FD (1 << 14) +#define DP83848_100BASE_TX_HD (1 << 13) +#define DP83848_10BASE_T_FD (1 << 12) +#define DP83848_10BASE_T_HD (1 << 11) +#define DP83848_MF_PREAMB_SUPPR (1 << 6) +#define DP83848_AUTONEG_COMP (1 << 5) +#define DP83848_RMT_FAULT (1 << 4) +#define DP83848_AUTONEG_ABILITY (1 << 3) +#define DP83848_LINK_STATUS (1 << 2) +#define DP83848_JABBER_DETECT (1 << 1) +#define DP83848_EXTEND_CAPAB (1 << 0) + +/*--definitions: DP83848_PHYID1 */ +#define DP83848_PHYID1_OUI 0x2000 +#define DP83848_PHYID2_OUI 0x5c90 + +/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ +#define DP83848_NP (1 << 15) +#define DP83848_ACK (1 << 14) +#define DP83848_RF (1 << 13) +#define DP83848_PAUSE (1 << 10) +#define DP83848_T4 (1 << 9) +#define DP83848_TX_FDX (1 << 8) +#define DP83848_TX_HDX (1 << 7) +#define DP83848_10_FDX (1 << 6) +#define DP83848_10_HDX (1 << 5) +#define DP83848_AN_IEEE_802_3 0x0001 + +/*--Bit definitions: DP83848_ANER */ +#define DP83848_PDF (1 << 4) +#define DP83848_LP_NP_ABLE (1 << 3) +#define DP83848_NP_ABLE (1 << 2) +#define DP83848_PAGE_RX (1 << 1) +#define DP83848_LP_AN_ABLE (1 << 0) + +/*--Bit definitions: DP83848_PHY_STAT */ +#define DP83848_RX_ERR_LATCH (1 << 13) +#define DP83848_POLARITY_STAT (1 << 12) +#define DP83848_FALSE_CAR_SENSE (1 << 11) +#define DP83848_SIG_DETECT (1 << 10) +#define DP83848_DESCRAM_LOCK (1 << 9) +#define DP83848_PAGE_RCV (1 << 8) +#define DP83848_PHY_RMT_FAULT (1 << 6) +#define DP83848_JABBER (1 << 5) +#define DP83848_AUTONEG_COMPLETE (1 << 4) +#define DP83848_LOOPBACK_STAT (1 << 3) +#define DP83848_DUPLEX (1 << 2) +#define DP83848_SPEED (1 << 1) +#define DP83848_LINK (1 << 0) diff --git a/include/exports.h b/include/exports.h index 0516da9..d6512cb 100644 --- a/include/exports.h +++ b/include/exports.h @@ -25,6 +25,9 @@ char *getenv (char *name); void setenv (char *varname, char *varvalue); long simple_strtol(const char *cp,char **endp,unsigned int base); int strcmp(const char * cs,const char * ct); +#ifdef CONFIG_HAS_UID +void forceenv (char *varname, char *varvalue); +#endif #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); diff --git a/include/fdt_support.h b/include/fdt_support.h index a276834..60fa423 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -38,5 +38,11 @@ int fdt_env(void *fdt); int fdt_bd_t(void *fdt); #endif +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd); +void ft_cpu_setup(void *blob, bd_t *bd); +void ft_pci_setup(void *blob, bd_t *bd); +#endif + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/libfdt.h b/include/libfdt.h index f8bac73..340e89d 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -77,7 +77,13 @@ int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, const char *name, int namelen); int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); -int fdt_path_offset(const void *fdt, const char *path); +int fdt_find_node_by_path(const void *fdt, const char *path); +int fdt_find_node_by_type(const void *fdt, int nodeoffset, const char *type); + +int fdt_node_is_compatible(const void *fdt, int nodeoffset, + const char *compat); +int fdt_find_compatible_node(const void *fdt, int nodeoffset, + const char *type, const char *compat); struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, const char *name, int *lenp); diff --git a/include/libfdt_env.h b/include/libfdt_env.h index e746314..78f7258 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -26,7 +26,7 @@ #include <asm/byteorder.h> #include <linux/string.h> -struct fdt_header *fdt; /* Pointer to the working fdt */ +extern struct fdt_header *fdt; /* Pointer to the working fdt */ #define fdt32_to_cpu(x) __be32_to_cpu(x) #define cpu_to_fdt32(x) __cpu_to_be32(x) diff --git a/include/spartan3.h b/include/spartan3.h index b14db03..65a3f5a 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -73,6 +73,13 @@ typedef struct { #define XILINX_XC3S4000_SIZE 11316864/8 #define XILINX_XC3S5000_SIZE 13271936/8 +/* Spartan-3E (v3.4) */ +#define XILINX_XC3S100E_SIZE 581344/8 +#define XILINX_XC3S250E_SIZE 1353728/8 +#define XILINX_XC3S500E_SIZE 2270208/8 +#define XILINX_XC3S1200E_SIZE 3841184/8 +#define XILINX_XC3S1600E_SIZE 5969696/8 + /* Descriptor Macros *********************************************************************/ /* Spartan-II devices */ @@ -100,4 +107,21 @@ typedef struct { #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie } + +/* Spartan-3E devices */ +#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } + +#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } + +#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } + +#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } + +#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } + #endif /* _SPARTAN3_H_ */ diff --git a/lib_arm/board.c b/lib_arm/board.c index 8f4e19b..d37e5da 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -364,6 +364,13 @@ void start_armboot (void) enable_interrupts (); /* Perform network card initialisation if necessary */ +#ifdef CONFIG_DRIVER_TI_EMAC +extern void dm644x_eth_set_mac_addr (const u_int8_t *addr); + if (getenv ("ethaddr")) { + dm644x_eth_set_mac_addr(gd->bd->bi_enetaddr); + } +#endif + #ifdef CONFIG_DRIVER_CS8900 cs8900_get_enetaddr (gd->bd->bi_enetaddr); #endif diff --git a/lib_avr32/Makefile b/lib_avr32/Makefile index cf20836..bb2938f 100644 --- a/lib_avr32/Makefile +++ b/lib_avr32/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(ARCH).a SOBJS = memset.o -COBJS = board.o interrupts.o avr32_linux.o div64.o +COBJS = board.o interrupts.o avr32_linux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/lib_generic/Makefile b/lib_generic/Makefile index b2091c5..bf37752 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)libgeneric.a COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ bzlib_randtable.o bzlib_huffman.o \ - crc32.o ctype.o display_options.o ldiv.o sha1.o \ + crc32.o ctype.o display_options.o div64.o ldiv.o sha1.o \ string.o vsprintf.o zlib.o SRCS := $(COBJS:.o=.c) diff --git a/lib_avr32/div64.c b/lib_generic/div64.c index 99726e3..d9951b5 100644 --- a/lib_avr32/div64.c +++ b/lib_generic/div64.c @@ -18,8 +18,6 @@ #include <linux/types.h> -#include <asm/div64.h> - uint32_t __div64_32(uint64_t *n, uint32_t base) { uint64_t rem = *n; diff --git a/libfdt/fdt.c b/libfdt/fdt.c index 212b838..1ee67ad 100644 --- a/libfdt/fdt.c +++ b/libfdt/fdt.c @@ -16,6 +16,9 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "config.h" +#if CONFIG_OF_LIBFDT + #include "libfdt_env.h" #include <fdt.h> @@ -83,3 +86,5 @@ int fdt_move(const void *fdt, void *buf, int bufsize) memmove(buf, fdt, fdt_totalsize(fdt)); return 0; } + +#endif /* CONFIG_OF_LIBFDT */ diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c index 4e2c325..ffd9209 100644 --- a/libfdt/fdt_ro.c +++ b/libfdt/fdt_ro.c @@ -16,6 +16,9 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "config.h" +#if CONFIG_OF_LIBFDT + #include "libfdt_env.h" #include <fdt.h> @@ -48,6 +51,33 @@ static int offset_streq(const void *fdt, int offset, } /* + * Checks if the property name matches. + */ +static int prop_name_eq(const void *fdt, int offset, const char *name, + struct fdt_property **prop, int *lenp) +{ + int namestroff, len; + + *prop = fdt_offset_ptr_typed(fdt, offset, *prop); + if (! *prop) + return -FDT_ERR_BADSTRUCTURE; + + namestroff = fdt32_to_cpu((*prop)->nameoff); + if (streq(fdt_string(fdt, namestroff), name)) { + len = fdt32_to_cpu((*prop)->len); + *prop = fdt_offset_ptr(fdt, offset, + sizeof(**prop) + len); + if (*prop) { + if (lenp) + *lenp = len; + return 1; + } else + return -FDT_ERR_BADSTRUCTURE; + } + return 0; +} + +/* * Return a pointer to the string at the given string offset. */ char *fdt_string(const void *fdt, int stroffset) @@ -56,6 +86,118 @@ char *fdt_string(const void *fdt, int stroffset) } /* + * Check if the specified node is compatible by comparing the tokens + * in its "compatible" property with the specified string: + * + * nodeoffset - starting place of the node + * compat - the string to match to one of the tokens in the + * "compatible" list. + */ +int fdt_node_is_compatible(const void *fdt, int nodeoffset, + const char *compat) +{ + const char* cp; + int cplen, len; + + cp = fdt_getprop(fdt, nodeoffset, "compatible", &cplen); + if (cp == NULL) + return 0; + while (cplen > 0) { + if (strncmp(cp, compat, strlen(compat)) == 0) + return 1; + len = strlen(cp) + 1; + cp += len; + cplen -= len; + } + + return 0; +} + +/* + * Find a node by its device type property. On success, the offset of that + * node is returned or an error code otherwise: + * + * nodeoffset - the node to start searching from or 0, the node you pass + * will not be searched, only the next one will; typically, + * you pass 0 to start the search and then what the previous + * call returned. + * type - the device type string to match against. + */ +int fdt_find_node_by_type(const void *fdt, int nodeoffset, const char *type) +{ + int offset, nextoffset; + struct fdt_property *prop; + uint32_t tag; + int len, ret; + + CHECK_HEADER(fdt); + + tag = fdt_next_tag(fdt, nodeoffset, &nextoffset, NULL); + if (tag != FDT_BEGIN_NODE) + return -FDT_ERR_BADOFFSET; + if (nodeoffset) + nodeoffset = 0; /* start searching with next node */ + + while (1) { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset, NULL); + + switch (tag) { + case FDT_BEGIN_NODE: + nodeoffset = offset; + break; + + case FDT_PROP: + if (nodeoffset == 0) + break; + ret = prop_name_eq(fdt, offset, "device_type", + &prop, &len); + if (ret < 0) + return ret; + else if (ret > 0 && + strncmp(prop->data, type, len - 1) == 0) + return nodeoffset; + break; + + case FDT_END_NODE: + case FDT_NOP: + break; + + case FDT_END: + return -FDT_ERR_NOTFOUND; + + default: + return -FDT_ERR_BADSTRUCTURE; + } + } +} + +/* + * Find a node based on its device type and one of the tokens in its its + * "compatible" property. On success, the offset of that node is returned + * or an error code otherwise: + * + * nodeoffset - the node to start searching from or 0, the node you pass + * will not be searched, only the next one will; typically, + * you pass 0 to start the search and then what the previous + * call returned. + * type - the device type string to match against. + * compat - the string to match to one of the tokens in the + * "compatible" list. + */ +int fdt_find_compatible_node(const void *fdt, int nodeoffset, + const char *type, const char *compat) +{ + int offset; + + offset = fdt_find_node_by_type(fdt, nodeoffset, type); + if (offset < 0 || fdt_node_is_compatible(fdt, offset, compat)) + return offset; + + return -FDT_ERR_NOTFOUND; +} + +/* * Return the node offset of the node specified by: * parentoffset - starting place (0 to start at the root) * name - name being searched for @@ -129,7 +271,7 @@ int fdt_subnode_offset(const void *fdt, int parentoffset, * Searches for the node corresponding to the given path and returns the * offset of that node. */ -int fdt_path_offset(const void *fdt, const char *path) +int fdt_find_node_by_path(const void *fdt, const char *path) { const char *end = path + strlen(path); const char *p = path; @@ -141,6 +283,10 @@ int fdt_path_offset(const void *fdt, const char *path) if (*path != '/') return -FDT_ERR_BADPATH; + /* Handle the root path: root offset is 0 */ + if (strcmp(path, "/") == 0) + return 0; + while (*p) { const char *q; @@ -184,7 +330,6 @@ struct fdt_property *fdt_get_property(const void *fdt, int level = 0; uint32_t tag; struct fdt_property *prop; - int namestroff; int offset, nextoffset; int err; @@ -224,24 +369,11 @@ struct fdt_property *fdt_get_property(const void *fdt, if (level != 0) continue; - err = -FDT_ERR_BADSTRUCTURE; - prop = fdt_offset_ptr_typed(fdt, offset, prop); - if (! prop) - goto fail; - namestroff = fdt32_to_cpu(prop->nameoff); - if (streq(fdt_string(fdt, namestroff), name)) { - /* Found it! */ - int len = fdt32_to_cpu(prop->len); - prop = fdt_offset_ptr(fdt, offset, - sizeof(*prop)+len); - if (! prop) - goto fail; - - if (lenp) - *lenp = len; - + err = prop_name_eq(fdt, offset, name, &prop, lenp); + if (err > 0) return prop; - } + else if (err < 0) + goto fail; break; case FDT_NOP: @@ -400,3 +532,6 @@ int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re) } return 0; } + +#endif /* CONFIG_OF_LIBFDT */ + diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c index aaafc53..693bfe4 100644 --- a/libfdt/fdt_rw.c +++ b/libfdt/fdt_rw.c @@ -16,6 +16,9 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "config.h" +#if CONFIG_OF_LIBFDT + #include "libfdt_env.h" #include <fdt.h> @@ -291,3 +294,5 @@ int fdt_pack(void *fdt) fdt_set_header(fdt, totalsize, _blob_data_size(fdt)); return 0; } + +#endif /* CONFIG_OF_LIBFDT */ diff --git a/libfdt/fdt_strerror.c b/libfdt/fdt_strerror.c index 7f231ce..b49c952 100644 --- a/libfdt/fdt_strerror.c +++ b/libfdt/fdt_strerror.c @@ -16,6 +16,9 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "config.h" +#if CONFIG_OF_LIBFDT + #include "libfdt_env.h" #include <fdt.h> @@ -62,3 +65,5 @@ const char *fdt_strerror(int errval) return "<unknown error>"; } + +#endif /* CONFIG_OF_LIBFDT */ diff --git a/libfdt/fdt_sw.c b/libfdt/fdt_sw.c index 672f4dd..c7eea8f 100644 --- a/libfdt/fdt_sw.c +++ b/libfdt/fdt_sw.c @@ -16,6 +16,9 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "config.h" +#if CONFIG_OF_LIBFDT + #include "libfdt_env.h" #include <fdt.h> @@ -224,3 +227,5 @@ int fdt_finish(void *fdt) fdt_set_header(fdt, magic, FDT_MAGIC); return 0; } + +#endif /* CONFIG_OF_LIBFDT */ diff --git a/libfdt/fdt_wip.c b/libfdt/fdt_wip.c index 2d2ed37..2d39aab 100644 --- a/libfdt/fdt_wip.c +++ b/libfdt/fdt_wip.c @@ -16,6 +16,9 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "config.h" +#if CONFIG_OF_LIBFDT + #include "libfdt_env.h" #include <fdt.h> @@ -135,3 +138,5 @@ int fdt_replace_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size) return 0; } + +#endif /* CONFIG_OF_LIBFDT */ @@ -464,6 +464,8 @@ extern int at91rm9200_miiphy_initialize(bd_t *bis); extern int emac4xx_miiphy_initialize(bd_t *bis); extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); +extern int dm644x_eth_miiphy_initialize(bd_t *bis); + int eth_initialize(bd_t *bis) { @@ -484,6 +486,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_NETARM) ns7520_miiphy_initialize(bis); #endif +#if defined(CONFIG_DRIVER_TI_EMAC) + dm644x_eth_miiphy_initialize(bis); +#endif return 0; } #endif |