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| author | Stefan Roese <sr@denx.de> | 2007-11-13 08:06:11 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-11-13 08:06:11 +0100 |
| commit | 7d0a4066b5a6b698e5fc1b66cfe9705774bbce93 (patch) | |
| tree | d0534c1cd8180f31be21635959859842a73a9f51 | |
| parent | 2d14684341109a69616e4d6016cd61402d55086f (diff) | |
| download | u-boot-imx-7d0a4066b5a6b698e5fc1b66cfe9705774bbce93.zip u-boot-imx-7d0a4066b5a6b698e5fc1b66cfe9705774bbce93.tar.gz u-boot-imx-7d0a4066b5a6b698e5fc1b66cfe9705774bbce93.tar.bz2 | |
ppc4xx: Fix 405EX PCIe UTLSET register setup
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | cpu/ppc4xx/4xx_pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index da179f9..de79552 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -480,8 +480,8 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) val = 0x00101000; SDR_WRITE(SDRN_PESDR_DLPSET(port), val); - SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222); - SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); |