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authorHaiying Wang <Haiying.Wang@freescale.com>2007-08-23 15:20:54 -0400
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-08-29 00:11:44 -0500
commit7a1ac419fa0d2d23ddd08bd61d16896a9f33c933 (patch)
tree9e08925fe043ec59a0c45c8b77aef10294731f59
parent94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b (diff)
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Enable L2 cache for MPC8568MDS board
The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
-rw-r--r--cpu/mpc85xx/cpu_init.c2
-rw-r--r--include/configs/MPC8568MDS.h6
2 files changed, 4 insertions, 4 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 7b99610..79ad20c 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -247,7 +247,7 @@ int cpu_init_r(void)
switch (cache_ctl & 0x30000000) {
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
- ver == SVR_8544) {
+ ver == SVR_8544 || ver == SVR_8568_E) {
printf ("L2 cache 512KB:");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index d5a14fc..ba744e9 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -63,9 +63,9 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.