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| author | Ye Li <ye.li@nxp.com> | 2017-03-07 16:30:50 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:04:43 +0800 |
| commit | 7901123eb0ed7e08e8a7e671a661b1ff8043bf2e (patch) | |
| tree | 5a91983927866f7ed2f5db1f6a1e690c3e32e5fb | |
| parent | 0912f86887a1138244d099a43fc49aa7cf931bf0 (diff) | |
| download | u-boot-imx-7901123eb0ed7e08e8a7e671a661b1ff8043bf2e.zip u-boot-imx-7901123eb0ed7e08e8a7e671a661b1ff8043bf2e.tar.gz u-boot-imx-7901123eb0ed7e08e8a7e671a661b1ff8043bf2e.tar.bz2 | |
MLK-14371 fsl_qspi: update the driver to support mx6ul and mx7d
After porting to v2017.03. we start to use community's QSPI driver,
not the one we maintained before in v2014-v2016.
The new QSPI driver only supports i.MX6SX. This patch adds support
for i.MX6UL and i.MX7D
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | drivers/spi/fsl_qspi.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index cdbe5d9..b1b5770 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define RX_BUFFER_SIZE 0x80 -#ifdef CONFIG_MX6SX +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7D) #define TX_BUFFER_SIZE 0x200 #else #define TX_BUFFER_SIZE 0x40 @@ -268,7 +268,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif -#ifdef CONFIG_MX6SX +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7D) /* * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. * So, Use IDATSZ in IPCR to determine the size and here set 0. @@ -611,6 +611,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) u32 mcr_reg, data, reg, status_reg, seqid; int i, size, tx_size; u32 to_or_from = 0; + u32 total; mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, @@ -661,6 +662,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) TX_BUFFER_SIZE : len; size = tx_size / 4; + total = size; for (i = 0; i < size; i++) { memcpy(&data, txbuf, 4); data = qspi_endian_xchg(data); @@ -674,8 +676,15 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) memcpy(&data, txbuf, size); data = qspi_endian_xchg(data); qspi_write32(priv->flags, ®s->tbdr, data); + total += 1; } +#if defined(CONFIG_MX7D) || defined(CONFIG_MX6UL) + /* iMX7D and MX6UL TXFIFO must be at least 16 bytes*/ + for (; total < 4; total++) + qspi_write32(priv->flags, ®s->tbdr, 0); +#endif + qspi_write32(priv->flags, ®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) @@ -1000,6 +1009,7 @@ static int fsl_qspi_probe(struct udevice *bus) } #endif + dm_spi_bus = bus->uclass_priv; dm_spi_bus->max_hz = plat->speed_hz; @@ -1071,7 +1081,7 @@ static int fsl_qspi_probe(struct udevice *bus) priv->amba_base[3] + amba_size_per_chip); break; default: - debug("Error: Unsupported chipselect number %u!\n", + printf("Error: Unsupported chipselect number %u!\n", priv->num_chipselect); qspi_module_disable(priv, 1); return -EINVAL; @@ -1207,9 +1217,12 @@ static const struct dm_spi_ops fsl_qspi_ops = { static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,vf610-qspi" }, { .compatible = "fsl,imx6sx-qspi" }, + { .compatible = "fsl,imx6ul-qspi" }, + { .compatible = "fsl,imx7d-qspi" }, { } }; + U_BOOT_DRIVER(fsl_qspi) = { .name = "fsl_qspi", .id = UCLASS_SPI, |