diff options
| author | Peng Fan <peng.fan@nxp.com> | 2016-02-24 18:13:04 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-03-25 15:00:12 +0800 |
| commit | 77a21ec5afd23bdf1a32bbe32f9be521b944ad2f (patch) | |
| tree | 1e724e14e38ecc896c87ed012b73c33ec847482e | |
| parent | 9811e3db89f535e54ae10a10caa660f8e6036270 (diff) | |
| download | u-boot-imx-77a21ec5afd23bdf1a32bbe32f9be521b944ad2f.zip u-boot-imx-77a21ec5afd23bdf1a32bbe32f9be521b944ad2f.tar.gz u-boot-imx-77a21ec5afd23bdf1a32bbe32f9be521b944ad2f.tar.bz2 | |
MLK-12436-14: imx: mx7dsdb: update ddr script
On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.
For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.
Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | board/freescale/mx7dsabresd/imximage.cfg | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg index 315cc29..08321ad 100644 --- a/board/freescale/mx7dsabresd/imximage.cfg +++ b/board/freescale/mx7dsabresd/imximage.cfg @@ -17,18 +17,23 @@ IMAGE_VERSION 2 /* - * Boot Device : sd + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor */ +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else BOOT_FROM sd +#endif #ifdef CONFIG_USE_PLUGIN /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000 #else -/* - * Secure boot support - */ + #ifdef CONFIG_SECURE_BOOT CSF CONFIG_CSF_SIZE #endif @@ -45,6 +50,12 @@ CSF CONFIG_CSF_SIZE * value value to be stored in the register */ +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + DATA 4 0x30340004 0x4F400005 DATA 4 0x30391000 0x00000002 @@ -82,7 +93,12 @@ DATA 4 0x30790000 0x17420f40 DATA 4 0x30790004 0x10210100 DATA 4 0x30790010 0x00060807 DATA 4 0x307900b0 0x1010007e -DATA 4 0x3079009c 0x00000d6e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 DATA 4 0x30790020 0x08080808 DATA 4 0x30790030 0x08080808 DATA 4 0x30790050 0x01000010 @@ -97,6 +113,7 @@ CHECK_BITS_SET 4 0x307900c4 0x1 DATA 4 0x307900c0 0x0e447304 DATA 4 0x307900c0 0x0e407304 + DATA 4 0x30384130 0x00000000 DATA 4 0x30340020 0x00000178 DATA 4 0x30384130 0x00000002 |