Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx/.git

30 files changed, 2102 insertions, 131 deletions

diff --git a/CHANGELOG b/CHANGELOG
index ed9ca83..3bfd48d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,69 @@
+commit f539b7ba7d7ef6dd187c8209609001cb1cd95e39
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Fri Jan 19 19:57:10 2007 +0100
+
+    [PATCH] SC3 board: added CFG_CMD_AUTOSCRIPT.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit d0b6e14087ddd8789f224a48e1d33f2a5df4d167
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Fri Jan 19 18:05:26 2007 +0100
+
+    [PATCH] CFI: define CFG_WRITE_SWAPPED_DATA for the CFI-Flash driver
+		 if you must swap the bytes between reading/writing.
+		 (Needed for the SC3 board)
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 9d8d5a5bfb64768f29a0cb47fc37cd6f4c40e276
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 16:05:47 2007 +0100
+
+    [PATCH] Add support for Prodrive SCPU (PDNB3 variant) board
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0057d758e3e874cbe7f24745d0cce8c1cb6c207e
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 11:54:52 2007 +0100
+
+    [PATCH] Update Prodrive P3Mx support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 34167a36c29ee946b727465db5c014746a08e978
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 11:48:10 2007 +0100
+
+    [PATCH] Add missing Taishan config file
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cb4820725e9fc409c5cbc8e83054a6ed522d2111
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Thu Jan 18 11:28:51 2007 +0100
+
+    [PATCH] Fix: Compilerwarnings for SC3 board.
+		 The EBC Configuration Register is now by CFG_EBC_CFG definable
+		 Added JFFS2 support for the SC3 board.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 5fb692cae57d1710c8f52a427cf7f39a37383fcd
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 10:25:34 2007 +0100
+
+    [PATCH] Add support for AMCC Taishan PPC440GX eval board
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6d3e0107235aa0e6a6dcb77f9884497280bf85ad
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Tue Jan 16 18:30:50 2007 +0100
+
+    Raname solidcard3 into sc3; add redundant env for sc3
+
 commit 1bbbbdd20fcec9933697000dcf55ff7972622596
 Author: Wolfgang Denk <wd@pollux.denx.de>
 Date:	Tue Jan 16 12:46:35 2007 +0100
diff --git a/MAINTAINERS b/MAINTAINERS
index ce20def..e9203eb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -292,6 +292,7 @@ Stefan Roese <sr@denx.de>
 	pcs440ep		PPC440EP
 	sequoia			PPC440EPx
 	sycamore		PPC405GPr
+	taishan			PPC440GX
 	walnut			PPC405GP
 	yellowstone		PPC440GR
 	yosemite		PPC440EP
@@ -464,6 +465,7 @@ Stefan Roese <sr@denx.de>
 
 	ixdpg425		xscale
 	pdnb3			xscale
+	scpu			xscale
 
 Robert Schwebel <r.schwebel@pengutronix.de>
 
diff --git a/MAKEALL b/MAKEALL
index 7ccaf91..40a5c77 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -86,9 +86,10 @@ LIST_4xx="	\
 	ocotea		OCRTC		ORSG		p3p440		\
 	PCI405		pcs440ep	PIP405		PLU405		\
 	PMC405		PPChameleonEVB	sbc405		sc3		\
-	sequoia		sequoia_nand	VOH405		VOM405		\
-	W7OLMC		W7OLMG		walnut		WUH405		\
-	XPEDITE1K	yellowstone	yosemite	yucca		\
+	sequoia		sequoia_nand	taishan		VOH405		\
+	VOM405		W7OLMC		W7OLMG		walnut		\
+	WUH405		XPEDITE1K	yellowstone	yosemite	\
+	yucca								\
 "
 
 #########################################################################
@@ -224,7 +225,7 @@ LIST_pxa="	\
 	xsengine	zylonite					\
 "
 
-LIST_ixp="ixdp425	ixdpg425	pdnb3"
+LIST_ixp="ixdp425	ixdpg425	pdnb3		scpu"
 
 
 LIST_arm="	\
diff --git a/Makefile b/Makefile
index 3e12982..b1952ed 100644
--- a/Makefile
+++ b/Makefile
@@ -1207,6 +1207,9 @@ sycamore_config:	unconfig
 	@echo "Configuring for sycamore board as subset of walnut..."
 	@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
 
+taishan_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
+
 VOH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
 
@@ -2063,8 +2066,15 @@ pleb2_config	:	unconfig
 logodl_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa logodl
 
-pdnb3_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm ixp pdnb3 prodrive
+pdnb3_config \
+scpu_config:    unconfig
+	@if [ "$(findstring scpu_,$@)" ] ; then \
+		echo "#define CONFIG_SCPU"      >>include/config.h ; \
+		echo "... on SCPU board variant" ; \
+	else \
+		>include/config.h ; \
+	fi
+	@$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive
 
 pxa255_idp_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
diff --git a/board/amcc/taishan/Makefile b/board/amcc/taishan/Makefile
new file mode 100644
index 0000000..462af00
--- /dev/null
+++ b/board/amcc/taishan/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o lcd.o update.o showinfo.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/taishan/config.mk b/board/amcc/taishan/config.mk
new file mode 100644
index 0000000..4eefff2
--- /dev/null
+++ b/board/amcc/taishan/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440GX Reference Platform (Taishan) board
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S
new file mode 100644
index 0000000..8db043b
--- /dev/null
+++ b/board/amcc/taishan/init.S
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+#define _256M       0x10000000
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c
new file mode 100644
index 0000000..8d2dce3
--- /dev/null
+++ b/board/amcc/taishan/lcd.c
@@ -0,0 +1,380 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_TAISHAN
+
+#define LCD_DELAY_NORMAL_US	100
+#define LCD_DELAY_NORMAL_MS	2
+#define LCD_CMD_ADDR		((volatile char *)(CFG_EBC2_LCM_BASE))
+#define LCD_DATA_ADDR		((volatile char *)(CFG_EBC2_LCM_BASE+1))
+#define LCD_BLK_CTRL		((volatile char *)(CFG_EBC1_FPGA_BASE+0x2))
+
+#define mdelay(t)	({unsigned long msec=(t); while (msec--) { udelay(1000);}})
+
+static int g_lcd_init_b = 0;
+static char *amcc_logo = "  AMCC TAISHAN  440GX EvalBoard";
+static char addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+	char cpld_val;
+
+	cpld_val = *LCD_BLK_CTRL;
+	*LCD_BLK_CTRL = val | cpld_val;
+}
+
+static void lcd_putc(char val)
+{
+	int i = 100;
+	char addr;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	addr = *LCD_CMD_ADDR;
+	udelay(LCD_DELAY_NORMAL_US);
+	if ((addr != 0) && (addr % 0x10 == 0)) {
+		addr_flag ^= 0x40;
+		*LCD_CMD_ADDR = addr_flag;
+	}
+
+	udelay(LCD_DELAY_NORMAL_US);
+	*LCD_DATA_ADDR = val;
+	udelay(LCD_DELAY_NORMAL_US);
+}
+
+static void lcd_puts(char *s)
+{
+	char *p = s;
+	int i = 100;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	while (*p)
+		lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+	int i = 100;
+	char *p = amcc_logo;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	*LCD_CMD_ADDR = 0x80;
+	while (*p)
+		lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+	if (g_lcd_init_b == 0) {
+		puts("LCD: ");
+		mdelay(100);	/* Waiting for the LCD initialize */
+
+		*LCD_CMD_ADDR = 0x38;	/*set function:8-bit,2-line,5x7 font type */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		*LCD_CMD_ADDR = 0x0f;	/*set display on,cursor on,blink on */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		*LCD_CMD_ADDR = 0x01;	/*display clear */
+		mdelay(LCD_DELAY_NORMAL_MS);
+
+		*LCD_CMD_ADDR = 0x06;	/*set entry */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		lcd_bl_ctrl(0x02);
+		lcd_put_logo();
+
+		puts("  ready\n");
+		g_lcd_init_b = 1;
+	}
+
+	return 0;
+}
+
+static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	lcd_init();
+	return 0;
+}
+
+static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	*LCD_CMD_ADDR = 0x01;
+	mdelay(LCD_DELAY_NORMAL_MS);
+	return 0;
+}
+static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_puts(argv[1]);
+	return 0;
+}
+static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_putc((char)argv[1][0]);
+	return 0;
+}
+static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong count;
+	ulong dir;
+	char cur_addr;
+
+	if (argc < 3) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+
+	count = simple_strtoul(argv[1], NULL, 16);
+	if (count > 31) {
+		printf("unable to shift > 0x20\n");
+		count = 0;
+	}
+
+	dir = simple_strtoul(argv[2], NULL, 16);
+	cur_addr = *LCD_CMD_ADDR;
+	udelay(LCD_DELAY_NORMAL_US);
+	if (dir == 0x0) {
+		if (addr_flag == 0x80) {
+			if (count >= (cur_addr & 0xf)) {
+				*LCD_CMD_ADDR = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+				count = 0;
+			}
+		} else {
+			if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+				*LCD_CMD_ADDR = 0x80;
+				addr_flag = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+				count = 0x0;
+			} else if (count >= (cur_addr & 0xf)) {
+				count -= cur_addr & 0xf;
+				*LCD_CMD_ADDR = 0x80 | 0xf;
+				addr_flag = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+			}
+		}
+	} else {
+		if (addr_flag == 0x80) {
+			if (count >= (0x1f - (cur_addr & 0xf))) {
+				count = 0x0;
+				addr_flag = 0xc0;
+				*LCD_CMD_ADDR = 0xc0 | 0xf;
+				udelay(LCD_DELAY_NORMAL_US);
+			} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+				count = count + (cur_addr & 0xf) - 0x0f;
+				addr_flag = 0xc0;
+				*LCD_CMD_ADDR = 0xc0;
+				udelay(LCD_DELAY_NORMAL_US);
+			}
+		} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+			count = 0x0;
+			*LCD_CMD_ADDR = 0xc0 | 0xf;
+			udelay(LCD_DELAY_NORMAL_US);
+		}
+	}
+
+	while (count--) {
+		if (dir == 0) {
+			*LCD_CMD_ADDR = 0x10;
+		} else {
+			*LCD_CMD_ADDR = 0x14;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd_test - lcd test display\n", NULL);
+U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd_cls - lcd clear display\n", NULL);
+U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
+	   "lcd_puts - display string on lcd\n",
+	   "<string> - <string> to be displayed\n");
+U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
+	   "lcd_putc - display char on lcd\n",
+	   "<char> - <char> to be displayed\n");
+U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
+	   "lcd_cur - shift cursor on lcd\n",
+	   "<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
+	   " <count> - 0~31\n" " <dir> - 0,backward; 1, forward\n");
+
+#if 0 /* test-only */
+void set_phy_loopback_mode(void)
+{
+	char devemac2[32];
+	char devemac3[32];
+
+	sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+	sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+#if 0
+	unsigned short reg_short;
+
+	miiphy_read(devemac2, 0x1, 1, &reg_short);
+	if (reg_short & 0x04) {
+		/*
+		 * printf("EMAC2 link up,do nothing\n");
+		 */
+	} else {
+		udelay(1000);
+		miiphy_write(devemac2, 0x1, 0, 0x6000);
+		udelay(1000);
+		miiphy_read(devemac2, 0x1, 0, &reg_short);
+		if (reg_short != 0x6000) {
+			printf
+			    ("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
+			     reg_short);
+		}
+	}
+
+	miiphy_read(devemac3, 0x3, 1, &reg_short);
+	if (reg_short & 0x04) {
+		/*
+		 * printf("EMAC3 link up,do nothing\n");
+		 */
+	} else {
+		udelay(1000);
+		miiphy_write(devemac3, 0x3, 0, 0x6000);
+		udelay(1000);
+		miiphy_read(devemac3, 0x3, 0, &reg_short);
+		if (reg_short != 0x6000) {
+			printf
+			    ("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
+			     reg_short);
+		}
+	}
+#else
+	/* Set PHY as LOOPBACK MODE, for Linux emac initializing */
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
+	udelay(1000);
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
+	udelay(1000);
+#endif	/* 0 */
+}
+
+void set_phy_normal_mode(void)
+{
+	char devemac2[32];
+	char devemac3[32];
+	unsigned short reg_short;
+
+	sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+	sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+	/* Set phy of EMAC2 */
+	miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, &reg_short);
+	reg_short &= ~(0x7);
+	reg_short |= 0x6;	/* RGMII DLL Delay */
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
+
+	miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, &reg_short);
+	reg_short &= ~(0x40);
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
+
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
+
+	/* Set phy of EMAC3 */
+	miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, &reg_short);
+	reg_short &= ~(0x7);
+	reg_short |= 0x6;	/* RGMII DLL Delay */
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
+
+	miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, &reg_short);
+	reg_short &= ~(0x40);
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
+
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
+}
+#endif	/* 0 - test only */
+
+static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	volatile unsigned int *GpioOr =
+		(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+	*GpioOr |= 0x00300000;
+	return 0;
+}
+
+static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	volatile unsigned int *GpioOr =
+		(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+	*GpioOr &= ~0x00300000;
+	return 0;
+}
+
+U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
+	   "ledon - led test light on\n", NULL);
+
+U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
+	   "ledoff - led test light off\n", NULL);
+#endif
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
new file mode 100644
index 0000000..57b9d1c
--- /dev/null
+++ b/board/amcc/taishan/showinfo.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+void show_reset_reg(void)
+{
+	unsigned long reg;
+
+	/* read clock regsiter */
+	printf("===== Display reset and initialize register Start =========\n");
+	mfclk(clk_pllc,reg);
+	printf("cpr_pllc   = %#010x\n",reg);
+
+	mfclk(clk_plld,reg);
+	printf("cpr_plld   = %#010x\n",reg);
+
+	mfclk(clk_primad,reg);
+	printf("cpr_primad = %#010x\n",reg);
+
+	mfclk(clk_primbd,reg);
+	printf("cpr_primbd = %#010x\n",reg);
+
+	mfclk(clk_opbd,reg);
+	printf("cpr_opbd   = %#010x\n",reg);
+
+	mfclk(clk_perd,reg);
+	printf("cpr_perd   = %#010x\n",reg);
+
+	mfclk(clk_mald,reg);
+	printf("cpr_mald   = %#010x\n",reg);
+
+	/* read sdr register */
+	mfsdr(sdr_ebc,reg);
+	printf("sdr_ebc    = %#010x\n",reg);
+
+	mfsdr(sdr_cp440,reg);
+	printf("sdr_cp440  = %#010x\n",reg);
+
+	mfsdr(sdr_xcr,reg);
+	printf("sdr_xcr    = %#010x\n",reg);
+
+	mfsdr(sdr_xpllc,reg);
+	printf("sdr_xpllc  = %#010x\n",reg);
+
+	mfsdr(sdr_xplld,reg);
+	printf("sdr_xplld  = %#010x\n",reg);
+
+	mfsdr(sdr_pfc0,reg);
+	printf("sdr_pfc0   = %#010x\n",reg);
+
+	mfsdr(sdr_pfc1,reg);
+	printf("sdr_pfc1   = %#010x\n",reg);
+
+	mfsdr(sdr_cust0,reg);
+	printf("sdr_cust0  = %#010x\n",reg);
+
+	mfsdr(sdr_cust1,reg);
+	printf("sdr_cust1  = %#010x\n",reg);
+
+	mfsdr(sdr_uart0,reg);
+	printf("sdr_uart0  = %#010x\n",reg);
+
+	mfsdr(sdr_uart1,reg);
+	printf("sdr_uart1  = %#010x\n",reg);
+
+	printf("===== Display reset and initialize register End   =========\n");
+}
+
+void show_xbridge_info(void)
+{
+	unsigned long reg;
+
+	printf("PCI-X chip control registers\n");
+	mfsdr(sdr_xcr, reg);
+	printf("sdr_xcr    = %#010x\n", reg);
+
+	mfsdr(sdr_xpllc, reg);
+	printf("sdr_xpllc  = %#010x\n", reg);
+
+	mfsdr(sdr_xplld, reg);
+	printf("sdr_xplld  = %#010x\n", reg);
+
+	printf("PCI-X Bridge Configure registers\n");
+	printf("PCIX0_VENDID            = %#06x\n", in16r(PCIX0_VENDID));
+	printf("PCIX0_DEVID             = %#06x\n", in16r(PCIX0_DEVID));
+	printf("PCIX0_CMD               = %#06x\n", in16r(PCIX0_CMD));
+	printf("PCIX0_STATUS            = %#06x\n", in16r(PCIX0_STATUS));
+	printf("PCIX0_REVID             = %#04x\n", in8(PCIX0_REVID));
+	printf("PCIX0_CACHELS           = %#04x\n", in8(PCIX0_CACHELS));
+	printf("PCIX0_LATTIM            = %#04x\n", in8(PCIX0_LATTIM));
+	printf("PCIX0_HDTYPE            = %#04x\n", in8(PCIX0_HDTYPE));
+	printf("PCIX0_BIST              = %#04x\n", in8(PCIX0_BIST));
+
+	printf("PCIX0_BAR0              = %#010x\n", in32r(PCIX0_BAR0));
+	printf("PCIX0_BAR1              = %#010x\n", in32r(PCIX0_BAR1));
+	printf("PCIX0_BAR2              = %#010x\n", in32r(PCIX0_BAR2));
+	printf("PCIX0_BAR3              = %#010x\n", in32r(PCIX0_BAR3));
+	printf("PCIX0_BAR4              = %#010x\n", in32r(PCIX0_BAR4));
+	printf("PCIX0_BAR5              = %#010x\n", in32r(PCIX0_BAR5));
+
+	printf("PCIX0_CISPTR            = %#010x\n", in32r(PCIX0_CISPTR));
+	printf("PCIX0_SBSSYSVID         = %#010x\n", in16r(PCIX0_SBSYSVID));
+	printf("PCIX0_SBSSYSID          = %#010x\n", in16r(PCIX0_SBSYSID));
+	printf("PCIX0_EROMBA            = %#010x\n", in32r(PCIX0_EROMBA));
+	printf("PCIX0_CAP               = %#04x\n", in8(PCIX0_CAP));
+	printf("PCIX0_INTLN             = %#04x\n", in8(PCIX0_INTLN));
+	printf("PCIX0_INTPN             = %#04x\n", in8(PCIX0_INTPN));
+	printf("PCIX0_MINGNT            = %#04x\n", in8(PCIX0_MINGNT));
+	printf("PCIX0_MAXLTNCY          = %#04x\n", in8(PCIX0_MAXLTNCY));
+
+	printf("PCIX0_BRDGOPT1          = %#010x\n", in32r(PCIX0_BRDGOPT1));
+	printf("PCIX0_BRDGOPT2          = %#010x\n", in32r(PCIX0_BRDGOPT2));
+
+	printf("PCIX0_POM0LAL           = %#010x\n", in32r(PCIX0_POM0LAL));
+	printf("PCIX0_POM0LAH           = %#010x\n", in32r(PCIX0_POM0LAH));
+	printf("PCIX0_POM0SA            = %#010x\n", in32r(PCIX0_POM0SA));
+	printf("PCIX0_POM0PCILAL        = %#010x\n", in32r(PCIX0_POM0PCIAL));
+	printf("PCIX0_POM0PCILAH        = %#010x\n", in32r(PCIX0_POM0PCIAH));
+	printf("PCIX0_POM1LAL           = %#010x\n", in32r(PCIX0_POM1LAL));
+	printf("PCIX0_POM1LAH           = %#010x\n", in32r(PCIX0_POM1LAH));
+	printf("PCIX0_POM1SA            = %#010x\n", in32r(PCIX0_POM1SA));
+	printf("PCIX0_POM1PCILAL        = %#010x\n", in32r(PCIX0_POM1PCIAL));
+	printf("PCIX0_POM1PCILAH        = %#010x\n", in32r(PCIX0_POM1PCIAH));
+	printf("PCIX0_POM2SA            = %#010x\n", in32r(PCIX0_POM2SA));
+
+	printf("PCIX0_PIM0SA            = %#010x\n", in32r(PCIX0_PIM0SA));
+	printf("PCIX0_PIM0LAL           = %#010x\n", in32r(PCIX0_PIM0LAL));
+	printf("PCIX0_PIM0LAH           = %#010x\n", in32r(PCIX0_PIM0LAH));
+	printf("PCIX0_PIM1SA            = %#010x\n", in32r(PCIX0_PIM1SA));
+	printf("PCIX0_PIM1LAL           = %#010x\n", in32r(PCIX0_PIM1LAL));
+	printf("PCIX0_PIM1LAH           = %#010x\n", in32r(PCIX0_PIM1LAH));
+	printf("PCIX0_PIM2SA            = %#010x\n", in32r(PCIX0_PIM1SA));
+	printf("PCIX0_PIM2LAL           = %#010x\n", in32r(PCIX0_PIM1LAL));
+	printf("PCIX0_PIM2LAH           = %#010x\n", in32r(PCIX0_PIM1LAH));
+
+	printf("PCIX0_XSTS              = %#010x\n", in32r(PCIX0_STS));
+}
+
+int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	show_xbridge_info();
+	return 0;
+}
+
+U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
+	   "xbriinfo  - Show PCIX bridge info\n", NULL);
+
+#define TAISHAN_PCI_DEV_ID0 0x800
+#define TAISHAN_PCI_DEV_ID1 0x1000
+
+void show_pcix_device_info(void)
+{
+	int ii;
+	int dev;
+	u8 capp;
+	u8 xcapid;
+	u16 status;
+	u16 xcommand;
+	u32 xstatus;
+
+	for (ii = 0; ii < 2; ii++) {
+		if (ii == 0)
+			dev = TAISHAN_PCI_DEV_ID0;
+		else
+			dev = TAISHAN_PCI_DEV_ID1;
+
+		pci_read_config_word(dev, PCI_STATUS, &status);
+		if (status & PCI_STATUS_CAP_LIST) {
+			pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
+
+			pci_read_config_byte(dev, (int)(capp), &xcapid);
+			if (xcapid == 0x07) {
+				pci_read_config_word(dev, (int)(capp + 2),
+						     &xcommand);
+				pci_read_config_dword(dev, (int)(capp + 4),
+						      &xstatus);
+				printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
+				       (ii + 1), xcommand, xstatus);
+			} else {
+				printf("BUS0 dev%d PCI-X CAP ID error,"
+				       "CAP=%#04x,XCAPID=%#04x\n",
+				       (ii + 1), capp, xcapid);
+			}
+		} else {
+			printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
+			       ii + 1);
+		}
+	}
+
+}
+
+int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
+			     char *argv[])
+{
+	show_pcix_device_info();
+	return 0;
+}
+
+U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
+	   "xdevinfo  - Show PCIX Device info\n", NULL);
+
+extern void show_reset_reg(void);
+
+int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	show_reset_reg();
+	return 0;
+}
+
+U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
+	   "resetinfo  - Show Reset REG info\n", NULL);
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
new file mode 100644
index 0000000..1a2e53b
--- /dev/null
+++ b/board/amcc/taishan/taishan.c
@@ -0,0 +1,331 @@
+/*
+ *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <ppc4xx_enet.h>
+
+#ifdef CFG_INIT_SHOW_RESET_REG
+void show_reset_reg(void);
+#endif
+
+int lcd_init(void);
+
+int board_early_init_f (void)
+{
+	unsigned long reg;
+	volatile unsigned int *GpioOdr;
+	volatile unsigned int *GpioTcr;
+	volatile unsigned int *GpioOr;
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*-------------------------------------------------------------------------+
+	  | 64MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | LCM. Initialize bank 2 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | TMP. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | Connector 4~7. Initialize bank 3~ 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb4ap,0);
+	mtebc(pb4cr,0);
+	mtebc(pb5ap,0);
+	mtebc(pb5cr,0);
+	mtebc(pb6ap,0);
+	mtebc(pb6cr,0);
+	mtebc(pb7ap,0);
+	mtebc(pb7cr,0);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
+	mtdcr (uicb0er, 0x00000000);	/* disable all */
+	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000);	/* */
+	mtdcr (uicb0tr, 0x00000000);	/* */
+	mtdcr (uicb0vr, 0x00000001);	/* */
+
+	/* Enable two GPIO 10~11 and TraceA signal */
+	mfsdr(sdr_pfc0,reg);
+	reg |= 0x00300000;
+	mtsdr(sdr_pfc0,reg);
+
+	mfsdr(sdr_pfc1,reg);
+	reg |= 0x00100000;
+	mtsdr(sdr_pfc1,reg);
+
+	/* Set GPIO 10 and 11 as output */
+	GpioOdr	= (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
+	GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
+	GpioOr  = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
+
+	*GpioOdr &= ~(0x00300000);
+	*GpioTcr |= 0x00300000;
+	*GpioOr  |= 0x00300000;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	lcd_init();
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+#ifdef CFG_INIT_SHOW_RESET_REG
+	show_reset_reg();
+#endif
+
+	return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x04000000;
+	uint *pend = (uint *) 0x0fc00000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The ocotea board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The ocotea board is always configured as host. */
+	return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return (ctrlc());
+}
+#endif
diff --git a/board/amcc/taishan/u-boot.lds b/board/amcc/taishan/u-boot.lds
new file mode 100644
index 0000000..664716e
--- /dev/null
+++ b/board/amcc/taishan/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/taishan/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c
new file mode 100644
index 0000000..ed2c196
--- /dev/null
+++ b/board/amcc/taishan/update.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#if defined(CONFIG_TAISHAN)
+
+const uchar bootstrap_buf[16] = {
+	0x86,
+	0x78,
+	0xc1,
+	0xa6,
+	0x09,
+	0x67,
+	0x04,
+	0x63,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00
+};
+
+static int update_boot_eeprom(void)
+{
+	ulong len = 0x10;
+	uchar chip = CFG_BOOTSTRAP_IIC_ADDR;
+	uchar *pbuf = (uchar *)bootstrap_buf;
+	int ii, jj;
+
+	for (ii = 0; ii < len; ii++) {
+		if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
+			printf("i2c_write failed\n");
+			return -1;
+		}
+
+		/* wait 10ms */
+		for (jj = 0; jj < 10; jj++)
+			udelay(1000);
+	}
+	return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	return update_boot_eeprom();
+}
+
+U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+	   "update_boot_eeprom  - update bootstrap eeprom content\n", NULL);
+#endif
diff --git a/board/idmr/flash.c b/board/idmr/flash.c
index ba9b009..33512b8 100644
--- a/board/idmr/flash.c
+++ b/board/idmr/flash.c
@@ -97,7 +97,7 @@ unsigned long flash_init (void)
 
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + 0x30000, &flash_info[0]);
+		       CFG_FLASH_BASE + 0x2ffff, &flash_info[0]);
 
 	return size;
 }
diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c
index 6cebd1a..d54ddaf 100644
--- a/board/prodrive/p3mx/p3mx.c
+++ b/board/prodrive/p3mx/p3mx.c
@@ -45,6 +45,7 @@
 #include "mpsc.h"
 #include "64460.h"
 #include "mv_regs.h"
+#include "p3mx.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -79,6 +80,7 @@ extern flash_info_t flash_info[];
 void board_prebootm_init (void);
 unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
 int display_mem_map (void);
+void set_led(int);
 
 /* ------------------------------------------------------------------------- */
 
@@ -246,7 +248,6 @@ int board_early_init_f (void)
 	 * that if it's not at the power-on location, it's where we put
 	 * it last time. (huber)
 	 */
-
 	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
 
 #ifdef CONFIG_PCI
@@ -287,6 +288,8 @@ int board_early_init_f (void)
 
 	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
 
+	set_led(LED_RED);
+
 	return 0;
 }
 
@@ -332,6 +335,7 @@ void after_reloc (ulong dest_addr, gd_t * gd)
 /*	display_mem_map(); */
 
 	/* now, jump to the main U-Boot board init code */
+	set_led(LED_GREEN);
 	board_init_r (gd, dest_addr);
 	/* NOTREACHED */
 }
@@ -356,15 +360,66 @@ int checkboard (void)
 	return (0);
 }
 
-/* utility functions */
-void debug_led (int led, int mode)
+void set_led(int col)
 {
+	int tmp;
+	int on_pin;
+	int off_pin;
+
+	/* Program Mpp[22] as Gpp[22]
+	 * Program Mpp[23] as Gpp[23]
+	 */
+	tmp = GTREGREAD(MPP_CONTROL2);
+	tmp &= 0x00ffffff;
+	GT_REG_WRITE(MPP_CONTROL2,tmp);
+
+	/* Program Gpp[22] and Gpp[23] as output
+	 */
+	tmp = GTREGREAD(GPP_IO_CONTROL);
+	tmp |= 0x00C00000;
+	GT_REG_WRITE(GPP_IO_CONTROL, tmp);
+
+	/* Program Gpp[22] and Gpp[23] as active high
+	 */
+	tmp = GTREGREAD(GPP_LEVEL_CONTROL);
+	tmp &= 0xff3fffff;
+	GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
+
+	switch(col) {
+	default:
+	case LED_OFF :
+		on_pin  = 0;
+		off_pin = ((1 << 23) | (1 << 22));
+		break;
+	case LED_RED :
+		on_pin  = (1 << 23);
+		off_pin = (1 << 22);
+		break;
+	case LED_GREEN :
+		on_pin  = (1 << 22);
+		off_pin = (1 << 23);
+		break;
+	case LED_ORANGE :
+		on_pin  = ((1 << 23) | (1 << 22));
+		off_pin = 0;
+		break;
+	}
+
+	/* Set output Gpp[22] and Gpp[23]
+	 */
+	tmp = GTREGREAD(GPP_VALUE);
+	tmp |= on_pin;
+	tmp &= ~off_pin;
+	GT_REG_WRITE(GPP_VALUE, tmp);
 }
 
 int display_mem_map (void)
 {
-	int i, j;
+	int i;
 	unsigned int base, size, width;
+#ifdef CONFIG_PCI
+	int j;
+#endif
 
 	/* SDRAM */
 	printf ("SD (DDR) RAM\n");
diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c
index 176252e..0464860 100644
--- a/board/prodrive/p3mx/sdram_init.c
+++ b/board/prodrive/p3mx/sdram_init.c
@@ -65,7 +65,7 @@ int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
 int memory_map_bank (unsigned int bankNo,
 		     unsigned int bankBase, unsigned int bankLength)
 {
-#ifdef MAP_PCI
+#if defined (MAP_PCI) && defined (CONFIG_PCI)
 	PCI_HOST host;
 #endif
 
@@ -80,7 +80,7 @@ int memory_map_bank (unsigned int bankNo,
 
 	memoryMapBank (bankNo, bankBase, bankLength);
 
-#ifdef MAP_PCI
+#if defined (MAP_PCI) && defined (CONFIG_PCI)
 	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
 		const int features =
 			PREFETCH_ENABLE |
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
index d0e5fe7..518ea9c 100644
--- a/board/prodrive/pdnb3/flash.c
+++ b/board/prodrive/pdnb3/flash.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
+#if !defined(CFG_FLASH_CFI_DRIVER)
+
 /*
  * include common flash code (for esd boards)
  */
@@ -83,3 +85,5 @@ unsigned long flash_init(void)
 
 	return size;
 }
+
+#endif /* CFG_FLASH_CFI_DRIVER */
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index d94896e..363a77d 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -354,6 +354,8 @@ int board_early_init_f (void)
 	initUsbHost (&cpldConfig_1);
 	writeb (cpldConfig_1, CPLD_CONTROL_1);
 #endif
+	/* FIXME: for what must we do this */
+	*(unsigned long *)0x79000080 = 0x0001;
 	return(0);
 }
 
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index aa6b2bd..ce59d39 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -49,11 +49,43 @@
 #endif
 
 #ifdef	CONFIG_M5271
+/*
+ * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
+ * determine which one we are running on, based on the Chip Identification
+ * Register (CIR).
+ */
 int checkcpu (void)
 {
 	char buf[32];
+	unsigned short cir;	/* Chip Identification Register */
+	unsigned short pin;	/* Part identification number */
+	unsigned char prn;	/* Part revision number */
+	char *cpu_model;
+
+	cir = mbar_readShort(MCF_CCM_CIR);
+	pin = cir >> MCF_CCM_CIR_PIN_LEN;
+	prn = cir & MCF_CCM_CIR_PRN_MASK;
+
+	switch (pin) {
+	case MCF_CCM_CIR_PIN_MCF5270:
+		cpu_model = "5270";
+		break;
+	case MCF_CCM_CIR_PIN_MCF5271:
+		cpu_model = "5271";
+		break;
+	default:
+		cpu_model = NULL;
+		break;
+	}
+
+	if (cpu_model)
+		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
+			cpu_model, prn, strmhz(buf, CFG_CLK));
+	else
+		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
+			" (PIN: 0x%x) rev. %hu, at %s MHz\n",
+			pin, prn, strmhz(buf, CFG_CLK));
 
-	printf ("CPU:   Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK));
 	return 0;
 }
 
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 38a1305..7134355 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 }
 
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) || defined (CONFIG_SOLIDCARD3)
+#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3))
 
 /*
  *As is these functs get called out of flash Not a horrible
@@ -406,7 +406,6 @@ static struct pci_controller hose = {
 	config_table: pci_405gp_config_table,
 };
 
-#ifndef CONFIG_SOLIDCARD3
 void pci_init_board(void)
 {
 	/*we want the ptrs to RAM not flash (ie don't use init list)*/
@@ -414,7 +413,6 @@ void pci_init_board(void)
 	hose.config_table = pci_405gp_config_table;
 	pci_405gp_init(&hose);
 }
-#endif
 
 #endif
 
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index 6130cd2..d6c4be5 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -26,10 +26,9 @@
 #include <common.h>
 #include <pci.h>
 
-#include "440spe_pcie.h"
+#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
 
-#if defined(CONFIG_440SPE)
-#if defined(CONFIG_PCI)
+#include "440spe_pcie.h"
 
 enum {
 	PTYPE_ENDPOINT		= 0x0,
@@ -958,5 +957,4 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
 	return 0;
 }
-#endif /* CONFIG_PCI */
-#endif /* CONFIG_440SPE */
+#endif /* CONFIG_440SPE && CONFIG_PCI */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 427ea94..4f55583 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -166,6 +166,11 @@ struct eth_device *emac0_dev = NULL;
 #define LAST_EMAC_NUM	1
 #endif
 
+/* normal boards start with EMAC0 */
+#if !defined(CONFIG_EMAC_NR_START)
+#define CONFIG_EMAC_NR_START	0
+#endif
+
 /*-----------------------------------------------------------------------------+
  * Prototypes and externals.
  *-----------------------------------------------------------------------------*/
@@ -601,6 +606,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			/* end Vitesse/Cicada errata */
 		}
 #endif
+
+#if defined(CONFIG_ET1011C_PHY)
+		/*
+		 * Agere ET1011c PHY needs to have an extended register whacked
+		 * for RGMII mode.
+		 */
+		if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
+			miiphy_read (dev->name, reg, 0x16, &reg_short);
+			reg_short &= ~(0x7);
+			reg_short |= 0x6;	/* RGMII DLL Delay*/
+			miiphy_write (dev->name, reg, 0x16, reg_short);
+
+			miiphy_read (dev->name, reg, 0x17, &reg_short);
+			reg_short &= ~(0x40);
+			miiphy_write (dev->name, reg, 0x17, reg_short);
+
+			miiphy_write(dev->name, reg, 0x1c, 0x74f0);
+		}
+#endif
+
 #endif
 		/* Start/Restart autonegotiation */
 		phy_setup_aneg (dev->name, reg);
@@ -643,8 +668,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 	if (hw_p->print_speed) {
 		hw_p->print_speed = 0;
-		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
-			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
+		printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
+			(int) speed, (duplex == HALF) ? "HALF" : "FULL",
+			hw_p->devnum);
 	}
 
 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@@ -1493,6 +1519,8 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 	struct eth_device *dev;
 	int eth_num = 0;
 	EMAC_4XX_HW_PST hw = NULL;
+	u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
+	u32 hw_addr[4];
 
 #if defined(CONFIG_440GX)
 	unsigned long pfc1;
@@ -1502,59 +1530,69 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 	pfc1 |= 0x01200000;
 	mtsdr (sdr_pfc1, pfc1);
 #endif
-	/* set phy num and mode */
-	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
-	bis->bi_phymode[0] = 0;
 
-#if defined(CONFIG_PHY1_ADDR)
-	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
-	bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
-	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
-	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
-	bis->bi_phymode[2] = 2;
-	bis->bi_phymode[3] = 2;
-
-	ppc_4xx_eth_setup_bridge(0, bis);
-#endif
+	/* first clear all mac-addresses */
+	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
+		memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
 
 	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
-
-		/* See if we can actually bring up the interface, otherwise, skip it */
 		switch (eth_num) {
 		default:		/* fall through */
 		case 0:
-			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enetaddr, 6);
+			hw_addr[eth_num] = 0x0;
 			break;
 #ifdef CONFIG_HAS_ETH1
 		case 1:
-			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet1addr, 6);
+			hw_addr[eth_num] = 0x100;
 			break;
 #endif
 #ifdef CONFIG_HAS_ETH2
 		case 2:
-			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet2addr, 6);
+			hw_addr[eth_num] = 0x400;
 			break;
 #endif
 #ifdef CONFIG_HAS_ETH3
 		case 3:
-			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet3addr, 6);
+			hw_addr[eth_num] = 0x600;
 			break;
 #endif
 		}
+	}
+
+	/* set phy num and mode */
+	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+	bis->bi_phymode[0] = 0;
+
+#if defined(CONFIG_PHY1_ADDR)
+	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+	bis->bi_phymode[1] = 0;
+#endif
+#if defined(CONFIG_440GX)
+	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
+	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
+	bis->bi_phymode[2] = 2;
+	bis->bi_phymode[3] = 2;
+
+	ppc_4xx_eth_setup_bridge(0, bis);
+#endif
+
+	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
+		/*
+		 * See if we can actually bring up the interface,
+		 * otherwise, skip it
+		 */
+		if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
+			bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
+			continue;
+		}
 
 		/* Allocate device structure */
 		dev = (struct eth_device *) malloc (sizeof (*dev));
@@ -1576,36 +1614,12 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 		}
 		memset(hw, 0, sizeof(*hw));
 
-		switch (eth_num) {
-		default:		/* fall through */
-		case 0:
-			hw->hw_addr = 0;
-			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
-			break;
-#ifdef CONFIG_HAS_ETH1
-		case 1:
-			hw->hw_addr = 0x100;
-			memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH2
-		case 2:
-			hw->hw_addr = 0x400;
-			memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH3
-		case 3:
-			hw->hw_addr = 0x600;
-			memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
-			break;
-#endif
-		}
-
+		hw->hw_addr = hw_addr[eth_num];
+		memcpy (dev->enetaddr, ethaddr[eth_num], 6);
 		hw->devnum = eth_num;
 		hw->print_speed = 1;
 
-		sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
+		sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
 		dev->priv = (void *) hw;
 		dev->init = ppc_4xx_eth_init;
 		dev->halt = ppc_4xx_eth_halt;
@@ -1663,7 +1677,6 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 	return (1);
 }
 
-
 #if !defined(CONFIG_NET_MULTI)
 void eth_halt (void) {
 	if (emac0_dev) {
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index e2aa867..ae24591 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -313,9 +313,8 @@ cpu_init_f (void)
 	mtebc(pb7cr, CFG_EBC_PB7CR);
 #endif
 
-#if defined (CONFIG_SOLIDCARD3)
-	mtebc(epcr, 0xb84ef000);
-	*(unsigned long *)0x79000080 = 0x0001;
+#if defined (CFG_EBC_CFG)
+	mtebc(epcr, CFG_EBC_CFG);
 #endif
 
 #if defined(CONFIG_WATCHDOG)
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 294b89c..d520cd3 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005-2006
+ * (C) Copyright 2005-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2006
@@ -32,9 +32,9 @@
 #include <asm/processor.h>
 #include "sdram.h"
 
-
 #ifdef CONFIG_SDRAM_BANK0
 
+#ifndef CONFIG_440
 
 #ifndef CFG_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
@@ -50,9 +50,6 @@ sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
 
 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
 
-
-#ifndef CONFIG_440
-
 #ifdef CFG_SDRAM_CASL
 static ulong ns2clks(ulong ns)
 {
@@ -221,6 +218,26 @@ void sdram_init(void)
 
 #else /* CONFIG_440 */
 
+/*
+ * Define some default values. Those can be overwritten in the
+ * board config file.
+ */
+
+#ifndef CFG_SDRAM_TABLE
+sdram_conf_t mb0cf[] = {
+	{(256 << 20), 13, 0x000C4001},	/* 256MB mode 3, 13x10(4)	*/
+	{(64 << 20),  12, 0x00082001}	/* 64MB mode 2, 12x9(4)		*/
+};
+#else
+sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+#endif
+
+#ifndef CFG_SDRAM0_TR0
+#define	CFG_SDRAM0_TR0		0x41094012
+#endif
+
+#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+
 #define NUM_TRIES 64
 #define NUM_READS 10
 
@@ -295,7 +312,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-
 #ifdef CONFIG_SDRAM_ECC
 static void ecc_init(ulong start, ulong size)
 {
@@ -351,7 +367,8 @@ long int initdram(int board_type)
 	int i;
 	int tr1_bank1;
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440SP)
 	/*
 	 * Soft-reset SDRAM controller.
 	 */
@@ -378,7 +395,7 @@ long int initdram(int board_type)
 		 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 		 */
 		mtsdram(mem_b0cr, mb0cf[i].reg);
-		mtsdram(mem_tr0, 0x41094012);
+		mtsdram(mem_tr0, CFG_SDRAM0_TR0);
 		mtsdram(mem_tr1, 0x80800800);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
 		mtsdram(mem_rtr, 0x04100000);	/* Interval 7.8µs @ 133MHz PLB	*/
 		mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM*/
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 8dc4499..696f9a4 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -40,10 +40,6 @@
 #include <environment.h>
 #ifdef	CFG_FLASH_CFI_DRIVER
 
-#if defined(CONFIG_SOLIDCARD3)
-#define __LITTLE_ENDIAN
-#endif
-
 /*
  * This file implements a Common Flash Interface (CFI) driver for U-Boot.
  * The width of the port and the width of the chips are determined at initialization.
@@ -58,6 +54,8 @@
  * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
  *   Device IDs, Publication Number 25538 Revision A, November 8, 2001
  *
+ * define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
+ * reading and writing ... (yes there is such a Hardware).
  */
 
 #ifndef CFG_FLASH_BANKS_LIST
@@ -260,7 +258,7 @@ inline uchar flash_read_uchar (flash_info_t * info, uint offset)
 	uchar *cp;
 
 	cp = flash_make_addr (info, 0, offset);
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	return (cp[0]);
 #else
 	return (cp[info->portwidth - 1]);
@@ -287,7 +285,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
 		debug ("addr[%x] = 0x%x\n", x, addr[x]);
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	retval = ((addr[(info->portwidth)] << 8) | addr[0]);
 #else
 	retval = ((addr[(2 * info->portwidth) - 1] << 8) |
@@ -319,7 +317,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
 		debug ("addr[%x] = 0x%x\n", x, addr[x]);
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
 		(addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
 #else
@@ -860,7 +858,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  */
 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 {
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 	unsigned short	w;
 	unsigned int	l;
 	unsigned long long ll;
@@ -871,7 +869,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 		cword->c = c;
 		break;
 	case FLASH_CFI_16BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 		w = c;
 		w <<= 8;
 		cword->w = (cword->w >> 8) | w;
@@ -880,7 +878,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 #endif
 		break;
 	case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 		l = c;
 		l <<= 24;
 		cword->l = (cword->l >> 8) | l;
@@ -889,7 +887,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 #endif
 		break;
 	case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 		ll = c;
 		ll <<= 56;
 		cword->ll = (cword->ll >> 8) | ll;
@@ -909,7 +907,7 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
 	int i;
 	uchar *cp = (uchar *) cmdbuf;
 
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	for (i = info->portwidth; i > 0; i--)
 #else
 	for (i = 1; i <= info->portwidth; i++)
@@ -1535,8 +1533,4 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 }
 #endif /* CFG_FLASH_USE_BUFFER_WRITE */
 
-#if defined(CONFIG_SOLIDCARD3)
-#undef __LITTLE_ENDIAN
-#endif
-
 #endif /* CFG_FLASH_CFI */
diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index 765414f..e0f02cf 100644
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -57,6 +57,12 @@
 #define MCF_GPIO_PAR_FECI2C			0x100047
 #define MCF_GPIO_PAR_UART			0x100048
 
+#define MCF_CCM_CIR				0x11000A
+#define MCF_CCM_CIR_PRN_MASK			0x3F
+#define MCF_CCM_CIR_PIN_LEN			6
+#define MCF_CCM_CIR_PIN_MCF5270			0x2e
+#define MCF_CCM_CIR_PIN_MCF5271			0x80
+
 #define MCF_GPIO_AD_ADDR23			0x80
 #define MCF_GPIO_AD_ADDR22			0x40
 #define MCF_GPIO_AD_ADDR21			0x20
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 48915b3..b1dbe2c 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -83,8 +83,8 @@
  */
 #define CONFIG_COMMANDS		((CONFIG_CMD_DFL		| \
 					CFG_CMD_PING		| \
-					CFG_CMD_NET		| \
-					CFG_CMD_MII)		& \
+					CFG_CMD_JFFS2		| \
+					CFG_CMD_NET)		& \
 					~(CFG_CMD_LOADS		| \
 						CFG_CMD_LOADB))
 
@@ -194,4 +194,20 @@
 
 /* Port configuration */
 #define CFG_FECI2C		0xF0
+
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=idmr-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=idmr-0:128k(u-boot),"	\
+						"64k(env),"	\
+						"640k(kernel),"	\
+						"2m(rootfs),"	\
+						"-(user)";
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#error MII commands don't work on iDMR board and sholud not be enabled.
+#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
+
 #endif /* _IDMR_H */
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 262e9d6..54462f0 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -168,10 +168,12 @@
 #define PCI_HOST_FORCE	1		/* configure as pci host	*/
 #define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
-#define CONFIG_PCI			/* include pci support		*/
+#undef CONFIG_PCI			/* include pci support		*/
+#ifdef CONFIG_PCI
 #define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
+#endif /* CONFIG_PCI */
 
 /* PCI MEMORY MAP section */
 #define CFG_PCI0_MEM_BASE	0x80000000
@@ -194,7 +196,6 @@
 #define CFG_PCI1_IO_SPACE_PCI	0x00000000
 
 #define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
-
 #define CFG_PCI_IDSEL 0x30
 
 #undef	CONFIG_BOOTARGS
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index ba6b113..2cc137c 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -71,12 +71,18 @@
 #define CONFIG_BAUDRATE         115200
 #define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
 
+#if defined(CONFIG_SCPU)
+#define CMD_NAND_ADD		0
+#else
+#define CMD_NAND_ADD		CFG_CMD_NAND
+#endif
+
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_NET	| \
 				CFG_CMD_MII	| \
-				CFG_CMD_NAND	| \
+				CMD_NAND_ADD	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_PING)
@@ -176,12 +182,20 @@
 
 #define CFG_FLASH_BASE          0x50000000
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#if defined(CONFIG_SCPU)
+#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
 #define CFG_MONITOR_LEN		(504 << 10)	/* Reserve 512 kB for Monitor	*/
+#endif
 
 /*
  * Expansion bus settings
  */
+#if defined(CONFIG_SCPU)
+#define CFG_EXP_CS0		0x94d23C42	/* 8bit, max size		*/
+#else
 #define CFG_EXP_CS0		0x94913C43	/* 8bit, max size		*/
+#endif
 #define CFG_EXP_CS1		0x85000043	/* 8bit, 512bytes		*/
 
 /*
@@ -194,6 +208,12 @@
 /*
  * FLASH and environment organization
  */
+#if defined(CONFIG_SCPU)
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+#endif
+
 #define FLASH_BASE0_PRELIM	CFG_FLASH_BASE		/* FLASH bank #0	*/
 
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
@@ -217,20 +237,27 @@
 
 #define	CFG_ENV_IS_IN_FLASH	1
 
+#if defined(CONFIG_SCPU)
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#else
 #define CFG_ENV_SECT_SIZE	0x1000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
 #define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#endif
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
 
 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
+#if !defined(CONFIG_SCPU)
 /*
  * NAND-FLASH stuff
  */
 #define CFG_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE		0x51000000	/* NAND FLASH Base Address	*/
+#endif
 
 /*
  * GPIO settings
@@ -284,9 +311,15 @@
 /*
  * I2C RTC
  */
+#if 0 /* test-only */
+#define CONFIG_RTC_DS1340	1
+#define CFG_I2C_RTC_ADDR	0x68
+#else
+/* M41T11 Serial Access Timekeeper(R) SRAM */
 #define CONFIG_RTC_M41T11	1
 #define CFG_I2C_RTC_ADDR	0x68
 #define CFG_M41T11_BASE_YEAR	1900	/* play along with the linux driver */
+#endif
 
 /*
  * Spartan3 FPGA configuration support
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 2d02782..b767449 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -108,7 +108,8 @@
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nand_args=setenv bootargs root=/dev/mtdblock4 rw\0"		\
+	"nand_args=setenv bootargs root=/dev/mtdblock5 rw"		\
+		"rootfstype=jffs2\0"					\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
@@ -118,6 +119,8 @@
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
 	"rootpath=/opt/eldk/ppc_4xx\0"					\
 	"bootfile=/tftpboot/sc3/uImage\0"				\
+	"u-boot=/tftpboot/sc3/u-boot.bin\0"				\
+	"setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0"	\
 	"kernel_addr=FFE08000\0"					\
 	""
 #undef CONFIG_BOOTCOMMAND
@@ -164,18 +167,20 @@
 
 #define CONFIG_COMMANDS	  \
 	   (CONFIG_CMD_DFL	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_NET | \
-				CFG_CMD_MII | \
-				CFG_CMD_PING | \
-				CFG_CMD_NAND | \
-				CFG_CMD_I2C | \
-				CFG_CMD_IDE | \
-				CFG_CMD_DATE | \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_CACHE  | \
-				CFG_CMD_ELF	)
+			CFG_CMD_AUTOSCRIPT	| \
+			CFG_CMD_PCI		| \
+			CFG_CMD_IRQ		| \
+			CFG_CMD_NET		| \
+			CFG_CMD_MII		| \
+			CFG_CMD_PING		| \
+			CFG_CMD_NAND		| \
+			CFG_CMD_JFFS2		| \
+			CFG_CMD_I2C		| \
+			CFG_CMD_IDE		| \
+			CFG_CMD_DATE		| \
+			CFG_CMD_DHCP		| \
+			CFG_CMD_CACHE		| \
+			CFG_CMD_ELF	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -382,6 +387,7 @@ extern unsigned long offsetOfEnvironment;
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CFG_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
 
 #define CFG_ENV_IS_IN_FLASH	1
 #if CFG_ENV_IS_IN_FLASH
@@ -404,6 +410,15 @@ extern unsigned long offsetOfEnvironment;
 #define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE		0x77D00000
 
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+
+/* No command line, one static partition Partition 3 contains jffs2 rootfs */
+#undef	CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00400000
+#define CONFIG_JFFS2_PART_OFFSET	0x00c00000
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  *
@@ -516,6 +531,8 @@ extern unsigned long offsetOfEnvironment;
 #undef CFG_EBC_PB7AP
 #undef CFG_EBC_PB7CR
 
+#define CFG_EBC_CFG    0xb84ef000
+
 #define CONFIG_SDRAM_BANK0	/* use the standard SDRAM initialization */
 #undef CONFIG_SPD_EEPROM
 
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
new file mode 100644
index 0000000..7ace397
--- /dev/null
+++ b/include/configs/taishan.h
@@ -0,0 +1,333 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * TAISHAN.h - configuration for AMCC 440GX Ref
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_TAISHAN		1	/* Board is taishan		*/
+#define CONFIG_440GX		1	/* Specifc GX support		*/
+#define CONFIG_4xx		1	/* ... PPC4xx family		*/
+#undef	CFG_DRAM_TEST			/* Disable-takes long time!	*/
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	0xfffc0000	/* start of monitor	*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE	0xe0000000	/* internal peripherals	*/
+#define CFG_ISRAM_BASE		0xc0000000	/* internal SRAM	*/
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+
+#define CFG_EBC0_FLASH_BASE	CFG_FLASH_BASE
+#define CFG_EBC1_FPGA_BASE	(CFG_PERIPHERAL_BASE + 0x01000000)
+#define CFG_EBC2_LCM_BASE	(CFG_PERIPHERAL_BASE + 0x02000000)
+#define CFG_EBC3_CONN_BASE	(CFG_PERIPHERAL_BASE + 0x08000000)
+
+#define CFG_GPIO_BASE		(CFG_PERIPHERAL_BASE + 0x00000700)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM*/
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_UART1_CONSOLE	1	/* use of UART1 as console	*/
+#define CONFIG_SERIAL_MULTI     1	/* enable serial multi support	*/
+#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	1024		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * E2PROM bootstrap configure value
+ *----------------------------------------------------------------------*/
+
+/*
+ * 800/133/66
+ * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
+ */
+
+/*
+ * 800/160/80
+ * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
+ */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
+#define	CFG_SDRAM0_TR0		0xC10A401A
+#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#undef CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CFG_BOOTSTRAP_IIC_ADDR	0x50
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=taishan\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/taishan/uImage\0"				\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc180000\0"					\
+	"load=tftp 100000 /tftpboot/taishan/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	"fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
+	"$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"dhcp=setenv bootargs $(bootargs) ip=dhcp\0"			\
+	"kozio=bootm 0xffe00000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_EMAC_NR_START	2	/* start with EMAC 2 (skip 0&1)	*/
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_ADDR	      	0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR      	0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY2_ADDR	0x1
+#define CONFIG_PHY3_ADDR	0x3
+#define CONFIG_ET1011C_PHY	1
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_DTT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_EEPRO100       1		/* include PCI EEPRO100		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */