summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2008-06-09 11:07:46 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-08-27 11:43:48 -0500
commit6fb1b7346849ccd0c20306143e334f5b76143070 (patch)
tree320b50edcc6655272ed8d5deb2818d370a076609
parentb5710d9974f6f0f3ddb4e67d6cccc262ab37049e (diff)
downloadu-boot-imx-6fb1b7346849ccd0c20306143e334f5b76143070.zip
u-boot-imx-6fb1b7346849ccd0c20306143e334f5b76143070.tar.gz
u-boot-imx-6fb1b7346849ccd0c20306143e334f5b76143070.tar.bz2
FSL DDR: Add e500 TLB helper for DDR code
Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--cpu/mpc85xx/tlb.c64
-rw-r--r--include/asm-ppc/mmu.h1
2 files changed, 65 insertions, 0 deletions
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 3d15d50..7ce7a14 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -90,3 +90,67 @@ void init_tlbs(void)
return ;
}
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+ unsigned int tlb_size;
+ unsigned int ram_tlb_index;
+ unsigned int ram_tlb_address;
+
+ /*
+ * Determine size of each TLB1 entry.
+ */
+ switch (memsize_in_meg) {
+ case 16:
+ case 32:
+ tlb_size = BOOKE_PAGESZ_16M;
+ break;
+ case 64:
+ case 128:
+ tlb_size = BOOKE_PAGESZ_64M;
+ break;
+ case 256:
+ case 512:
+ tlb_size = BOOKE_PAGESZ_256M;
+ break;
+ case 1024:
+ case 2048:
+ if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
+ tlb_size = BOOKE_PAGESZ_1G;
+ else
+ tlb_size = BOOKE_PAGESZ_256M;
+ break;
+ default:
+ puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
+ " and 2G are supported.\n");
+
+ /*
+ * The memory was not able to be mapped.
+ * Default to a small size.
+ */
+ tlb_size = BOOKE_PAGESZ_64M;
+ memsize_in_meg = 64;
+ break;
+ }
+
+ /*
+ * Configure DDR TLB1 entries.
+ * Starting at TLB1 8, use no more than 8 TLB1 entries.
+ */
+ ram_tlb_index = 8;
+ ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+ while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
+ && ram_tlb_index < 16) {
+ set_tlb(1, ram_tlb_address, ram_tlb_address,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, ram_tlb_index, tlb_size, 1);
+
+ ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
+ ram_tlb_index++;
+ }
+
+ /*
+ * Confirm that the requested amount of memory was mapped.
+ */
+ return memsize_in_meg;
+}
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 050a7b6..8975e6c 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -431,6 +431,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
extern void disable_tlb(u8 esel);
extern void invalidate_tlb(u8 tlb);
extern void init_tlbs(void);
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
{ .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \