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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-04-16 21:30:48 +0200
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-04-16 21:30:48 +0200
commit6ebff365eb63093ca35b687316002535c6a18820 (patch)
treeffb82ebd1d7cc6066ca067aad5097193386841e5
parentf0a2c7b4b64eacd06bb272856bcc056be8719f5a (diff)
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at91sam9/at91cap: fix CONFIG_SYS_HZ to 1000
The timer has been rewrote with a precision at ~0,18% Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Tested-by: Sergey Lapin <slapin@ossfans.org> Tested-by: Eric BENARD <ebenard@free.fr>
-rw-r--r--cpu/arm926ejs/at91/timer.c82
-rw-r--r--include/configs/afeb9260.h2
-rw-r--r--include/configs/at91cap9adk.h2
-rw-r--r--include/configs/at91sam9260ek.h2
-rw-r--r--include/configs/at91sam9261ek.h2
-rw-r--r--include/configs/at91sam9263ek.h2
-rw-r--r--include/configs/at91sam9rlek.h2
-rw-r--r--include/configs/pm9263.h2
8 files changed, 51 insertions, 45 deletions
diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c
index fec545b..c84cb5e 100644
--- a/cpu/arm926ejs/at91/timer.c
+++ b/cpu/arm926ejs/at91/timer.c
@@ -27,7 +27,9 @@
#include <asm/arch/at91_pit.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
#include <asm/arch/io.h>
+#include <div64.h>
/*
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
@@ -36,11 +38,26 @@
#define TIMER_LOAD_VAL 0xfffff
#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
-#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
-#define TICKS_TO_USEC(ticks) ((ticks) / 6)
-ulong get_timer_masked(void);
-ulong resettime;
+static ulong timestamp;
+static ulong lastinc;
+static ulong timer_freq;
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, timer_freq);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= timer_freq;
+ do_div(usec, 1000000);
+
+ return usec;
+}
/* nothing really to do with interrupts, just starts up a counter. */
int timer_init(void)
@@ -56,41 +73,49 @@ int timer_init(void)
reset_timer_masked();
+ timer_freq = get_mck_clk_rate() >> 4;
+
return 0;
}
/*
* timer without interrupts
*/
-
-static inline ulong get_timer_raw(void)
+unsigned long long get_ticks(void)
{
ulong now = READ_TIMER;
- if (now >= resettime)
- return now - resettime;
- else
- return 0xFFFFFFFFUL - (resettime - now) ;
+ if (now >= lastinc) /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (now - lastinc);
+ else /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ lastinc = now;
+ return timestamp;
}
void reset_timer_masked(void)
{
- resettime = READ_TIMER;
+ /* reset time */
+ lastinc = READ_TIMER; /* capture current incrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked(void)
{
- return TICKS_TO_USEC(get_timer_raw());
-
+ return tick_to_time(get_ticks());
}
-void udelay_masked(unsigned long usec)
+void udelay(unsigned long usec)
{
- ulong tmp;
+ unsigned long long tmp;
+ ulong tmo;
- tmp = get_timer(0);
- while (get_timer(tmp) < usec) /* our timer works in usecs */
- ; /* NOP */
+ tmo = usec_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
}
void reset_timer(void)
@@ -100,26 +125,7 @@ void reset_timer(void)
ulong get_timer(ulong base)
{
- ulong now = get_timer_masked();
-
- if (now >= base)
- return now - base;
- else
- return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ;
-}
-
-void udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
+ return get_timer_masked () - base;
}
/*
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index d637a94..c5134a2 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -28,7 +28,7 @@
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
-#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
#define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index c61af08..b2e6d7d 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -30,7 +30,7 @@
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91CAP9"
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index b6e2edf..e46c9d6 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -29,7 +29,7 @@
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 7ec171c..fdaa71c 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -30,7 +30,7 @@
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9261"
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 34c7521..d03ecee 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -30,7 +30,7 @@
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9263"
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
-#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 2ccf958..846d165 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -30,7 +30,7 @@
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9RL"
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 9ae737f..0db17b3 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -38,7 +38,7 @@
#define MAIN_PLL_DIV 2 /* 2 or 4 */
#define AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_HZ 1000000
+#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/