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authorTirumala R Marri <tmarri@amcc.com>2008-08-21 21:54:53 -0700
committerStefan Roese <sr@denx.de>2008-08-22 10:31:41 +0200
commit5d4b3d2b31e58fcb2d4bd10af762f5ff41b229fd (patch)
treef52b68eda4ff6b74d85c69d2c0e895040ab0abf7
parentf556483734126793522fb7a8cf36af90da78f084 (diff)
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ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fix
During recent PCI-E tests it has been found that current driverl level and de-emphasis values are not set correctly. After sweeping throgh all de-ephasis values, it was found that 0x130 is a right value. Where 0x13 is driver level and 0 is de-emphasis. Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--cpu/ppc4xx/4xx_pcie.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 9803fcc..0aadc06 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -638,7 +638,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
switch (port) {
case 0:
SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
- SDR_WRITE(PESDR0_L0DRV, 0x00000136);
+ SDR_WRITE(PESDR0_L0DRV, 0x00000130);
SDR_WRITE(PESDR0_L0CLK, 0x00000006);
SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
@@ -649,10 +649,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L0DRV, 0x00000136);
- SDR_WRITE(PESDR1_L1DRV, 0x00000136);
- SDR_WRITE(PESDR1_L2DRV, 0x00000136);
- SDR_WRITE(PESDR1_L3DRV, 0x00000136);
+ SDR_WRITE(PESDR1_L0DRV, 0x00000130);
+ SDR_WRITE(PESDR1_L1DRV, 0x00000130);
+ SDR_WRITE(PESDR1_L2DRV, 0x00000130);
+ SDR_WRITE(PESDR1_L3DRV, 0x00000130);
SDR_WRITE(PESDR1_L0CLK, 0x00000006);
SDR_WRITE(PESDR1_L1CLK, 0x00000006);
SDR_WRITE(PESDR1_L2CLK, 0x00000006);