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| author | Lily Zhang <r58066@freescale.com> | 2009-12-25 16:21:56 +0800 |
|---|---|---|
| committer | Lily Zhang <r58066@freescale.com> | 2009-12-25 16:24:49 +0800 |
| commit | 5c5128b60555aa6a793eac9e507d5c984bd5f3ec (patch) | |
| tree | 9eb69bee4da868388f87cf3c77407313e8d88ddc | |
| parent | 67b3137678e0ef7f405130b76671f35d0cba4617 (diff) | |
| download | u-boot-imx-5c5128b60555aa6a793eac9e507d5c984bd5f3ec.zip u-boot-imx-5c5128b60555aa6a793eac9e507d5c984bd5f3ec.tar.gz u-boot-imx-5c5128b60555aa6a793eac9e507d5c984bd5f3ec.tar.bz2 | |
ENGR00119591 Fix SPI-NOR reset issue
Add the workaround for ENGcm09397: reconfigure eCSPI SS signal
as GPIO before reset.
Signed-off-by: Lily Zhang <r58066@freescale.com>
| -rw-r--r-- | cpu/arm_cortexa8/mx51/interrupts.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c index 9758bef..5212a42 100644 --- a/cpu/arm_cortexa8/mx51/interrupts.c +++ b/cpu/arm_cortexa8/mx51/interrupts.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/mx51.h> /* nothing really to do with interrupts, just starts up a counter. */ @@ -34,5 +35,13 @@ int interrupt_init(void) void reset_cpu(ulong addr) { + /* workaround for ENGcm09397 - Fix SPI NOR reset issue*/ + /* de-select SS0 of instance: eCSPI1 */ + writel(0x3, IOMUXC_BASE_ADDR + 0x218); + writel(0x85, IOMUXC_BASE_ADDR + 0x608); + /* de-select SS1 of instance: ecspi1 */ + writel(0x3, IOMUXC_BASE_ADDR + 0x21C); + writel(0x85, IOMUXC_BASE_ADDR + 0x60C); + __REG16(WDOG1_BASE_ADDR) = 4; } |