diff options
| author | Aneesh V <aneesh@ti.com> | 2011-07-21 09:29:23 -0400 |
|---|---|---|
| committer | U-Boot <uboot@aari01-12.(none)> | 2011-08-03 12:49:20 +0200 |
| commit | 5ab12a9eeb7c8c1ca331685d1babca6081c7718f (patch) | |
| tree | fd11367f2ddd52657ce597fbc4c48e9400915d24 | |
| parent | 3decb14abe76d244ba98fd158ef95f89e7e37d70 (diff) | |
| download | u-boot-imx-5ab12a9eeb7c8c1ca331685d1babca6081c7718f.zip u-boot-imx-5ab12a9eeb7c8c1ca331685d1babca6081c7718f.tar.gz u-boot-imx-5ab12a9eeb7c8c1ca331685d1babca6081c7718f.tar.bz2 | |
omap4: add omap4460 revision detection
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/board.c | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/omap4.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv7.h | 1 |
3 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 2e5739a..17e731a 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -140,6 +140,9 @@ static void init_omap4_revision(void) case MIDR_CORTEX_A9_R1P3: *omap4_revision = OMAP4430_ES2_3; break; + case MIDR_CORTEX_A9_R2P10: + *omap4_revision = OMAP4460_ES1_0; + break; default: *omap4_revision = OMAP4430_SILICON_ID_INVALID; break; diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 563544f..7ff46d7 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -143,6 +143,7 @@ struct s32ktimer { #define OMAP4430_ES2_1 0x44300210 #define OMAP4430_ES2_2 0x44300220 #define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index b5784d8..9adc563 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -29,6 +29,7 @@ #define MIDR_CORTEX_A9_R0P1 0x410FC091 #define MIDR_CORTEX_A9_R1P2 0x411FC092 #define MIDR_CORTEX_A9_R1P3 0x411FC093 +#define MIDR_CORTEX_A9_R2P10 0x412FC09A /* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 |