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| author | Anatolij Gustschin <agust@denx.de> | 2008-09-17 11:45:51 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-09-22 21:46:56 +0200 |
| commit | 562788b0a303f3528b920d81f547f5ca77ba528e (patch) | |
| tree | 91ded2ec7ae8f23422185f5a6ed1e8588c503a1b | |
| parent | 3a9a000d9fba5a127786c8a859d654ba3721917b (diff) | |
| download | u-boot-imx-562788b0a303f3528b920d81f547f5ca77ba528e.zip u-boot-imx-562788b0a303f3528b920d81f547f5ca77ba528e.tar.gz u-boot-imx-562788b0a303f3528b920d81f547f5ca77ba528e.tar.bz2 | |
socrates: fix SPD EEPROM address
Commit be0bd8234b9777ecd63c4c686f72af070d886517
changed SPD EEPROM address to 0x51 and DDR SDRAM
detection stopped working. Change this address
back to 0x50.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
| -rw-r--r-- | include/configs/socrates.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 0135ac8..28e8fd2 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -117,7 +117,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ |