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| author | Thierry Reding <treding@nvidia.com> | 2015-08-20 11:52:13 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-10-15 14:41:20 +0200 |
| commit | 55aa0bed9803b8a5bd3e462fd712741c2e1cff1b (patch) | |
| tree | cb2cd57df00757616ce43ac3fe1e21cc6876d6a7 | |
| parent | 13a3972585af60ec367d209cedbd3601e0c77467 (diff) | |
| download | u-boot-imx-55aa0bed9803b8a5bd3e462fd712741c2e1cff1b.zip u-boot-imx-55aa0bed9803b8a5bd3e462fd712741c2e1cff1b.tar.gz u-boot-imx-55aa0bed9803b8a5bd3e462fd712741c2e1cff1b.tar.bz2 | |
armv8/mmu: Clean up TCR programming
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0c928d4..a1c3c06 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -103,9 +103,9 @@ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ -/* PTWs cacheable, inner/outer WBWA and non-shareable */ +/* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ + TCR_SHARED_INNER | \ TCR_ORGN_WBWA | \ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) |