diff options
| author | Minkyu Kang <mk7.kang@samsung.com> | 2015-10-22 14:51:58 +0900 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-11-02 10:38:22 +0900 |
| commit | 55a70c51acd20d52badbb0683699b7a11fee5f44 (patch) | |
| tree | f7e61e3dd7eb66df43808048de4e793e2dd188a4 | |
| parent | 96094d4c46ba6f0402fd6add9b246380dae54536 (diff) | |
| download | u-boot-imx-55a70c51acd20d52badbb0683699b7a11fee5f44.zip u-boot-imx-55a70c51acd20d52badbb0683699b7a11fee5f44.tar.gz u-boot-imx-55a70c51acd20d52badbb0683699b7a11fee5f44.tar.bz2 | |
arm: exynos: clean up checkpatch issues
This patch will fix these checkpatch issues.
ERROR: Macros with complex values should be enclosed in parentheses
+#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+ || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
ERROR: space prohibited before that ',' (ctx:WxW)
+ writel(val , &drex0->concontrol);
^
ERROR: space prohibited before that ',' (ctx:WxW)
+ writel(val , &drex1->concontrol);
^
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| -rw-r--r-- | arch/arm/mach-exynos/dmc_init_ddr3.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index 7c0b12a..25a9df9 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -20,8 +20,8 @@ #define TIMEOUT_US 10000 #define NUM_BYTE_LANES 4 #define DEFAULT_DQS 8 -#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ - || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) +#define DEFAULT_DQS_X4 ((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)) #ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) @@ -856,10 +856,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) */ val = readl(&drex0->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex0->concontrol); + writel(val, &drex0->concontrol); val = readl(&drex1->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex1->concontrol); + writel(val, &drex1->concontrol); return 0; } |