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authormario.six@gdsys.cc <mario.six@gdsys.cc>2016-05-25 15:15:22 +0200
committerYork Sun <york.sun@nxp.com>2016-06-03 22:14:12 -0700
commit51781783c59ad0080621d777579eb8acd14aa0ed (patch)
tree9bc3d558f520e04d407b5b582a98b525e4f1e832
parent53ecdfb92034ce836ec94ba33ba0d8d27ea3c16c (diff)
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dm: gpio: Implement open drain for MPC85XX GPIO
This patch implements the open-drain setting feature for the MPC85XX GPIO controller. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/mpc85xx_gpio.c41
2 files changed, 44 insertions, 3 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b674a47..8595e2e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -193,9 +193,9 @@ config MPC85XX_GPIO
configurable to match the actual GPIO count of the SoC (e.g. the
32/32/23 banks of the P1022 SoC).
- The standard functions of input/output mode, and output value setting
- are supported; the open-drain capability of the controller is not
- supported yet.
+ Aside from the standard functions of input/output mode, and output
+ value setting, the open-drain feature, which can configure individual
+ GPIOs to work as open-drain outputs, is supported.
The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
index 17755df..04773e2 100644
--- a/drivers/gpio/mpc85xx_gpio.c
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -73,6 +73,25 @@ static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
setbits_be32(&base->gpdir, gpios);
}
+static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpodr) & mask;
+}
+
+static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+ gpios)
+{
+ /* GPODR register 1 -> open drain on */
+ setbits_be32(&base->gpodr, gpios);
+}
+
+static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
+ u32 gpios)
+{
+ /* GPODR register 0 -> open drain off (actively driven) */
+ clrbits_be32(&base->gpodr, gpios);
+}
+
static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
{
struct mpc85xx_gpio_data *data = dev_get_priv(dev);
@@ -115,6 +134,26 @@ static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
}
}
+static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+ return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+ if (value) {
+ mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
+ } else {
+ mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
+ }
+ return 0;
+}
+
static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
{
struct mpc85xx_gpio_data *data = dev_get_priv(dev);
@@ -168,6 +207,8 @@ static const struct dm_gpio_ops gpio_mpc85xx_ops = {
.direction_output = mpc85xx_gpio_direction_output,
.get_value = mpc85xx_gpio_get_value,
.set_value = mpc85xx_gpio_set_value,
+ .get_open_drain = mpc85xx_gpio_get_open_drain,
+ .set_open_drain = mpc85xx_gpio_set_open_drain,
.get_function = mpc85xx_gpio_get_function,
};