ARM: UniPhier: fix typos in comments

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

2 files changed, 13 insertions, 12 deletions

diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 3a3ada8..4a23ea4 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -25,8 +25,8 @@ ENTRY(lowlevel_init)
 	 * First we need to turn on MMU and Dcache again to get back
 	 * data access to L2.
 	 */
-	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR (System Contrl Register)
-	orr	r0, r0, #(CR_C | CR_M)		@ enable MMU and Dcache
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
+	orr	r0, r0, #(CR_C | CR_M)	@ enable MMU and Dcache
 	mcr	p15, 0, r0, c1, c0, 0
 
 #ifdef CONFIG_DEBUG_LL
@@ -41,7 +41,7 @@ ENTRY(lowlevel_init)
 	ldr	r3, =init_page_table	@ page table must be 16KB aligned
 
 	/* Disable MMU and Dcache before switching Page Table */
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
 	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
 	mcr	p15, 0, r0, c1, c0, 0
 
@@ -55,7 +55,7 @@ ENTRY(lowlevel_init)
 	 * bit[7]  EXCL (Exclusive cache bit)
 	 * bit[6]  SMP
 	 * bit[3]  Write full line of zeros mode
-	 * bit[2]  L1 Prefetch enable
+	 * bit[2]  L1 prefetch enable
 	 * bit[1]  L2 prefetch enable
 	 * bit[0]  FW (Cache and TLB maintenance broadcast)
 	 */
@@ -81,7 +81,7 @@ primary_cpu:
 	ldr	r0, =_start		@ entry for the secondary CPU
 	str	r0, [r1]
 	ldr	r0, [r1]		@ make sure str is complete before sev
-	sev				@ kick the sedoncary CPU
+	sev				@ kick the secondary CPU
 	mrc	p15, 4, r1, c15, c0, 0	@ Configuration Base Address Register
 	bfc	r1, #0, #13		@ clear bit 12-0
 	mov	r0, #-1
@@ -118,7 +118,7 @@ ENTRY(enable_mmu)
 	 * TLBs was already invalidated in "../start.S"
 	 * So, we don't need to invalidate it here.
 	 */
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
 	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
 	mcr	p15, 0, r0, c1, c0, 0
 
@@ -155,7 +155,7 @@ ENTRY(setup_init_ram)
 	ldr	r1, = SSCOPPQSEF
 	ldr	r0, [r1]
 	cmp	r0, #0			@ check if the command is successfully set
-	bne	0b			@ try again if an error occurres
+	bne	0b			@ try again if an error occurs
 
 	ldr	r1, = SSCOLPQS
 1:
diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c
index e7b4158..77cc794 100644
--- a/arch/arm/mach-uniphier/support_card.c
+++ b/arch/arm/mach-uniphier/support_card.c
@@ -1,6 +1,7 @@
 /*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -94,7 +95,7 @@ void support_card_init(void)
 	/*
 	 * After power on, we need to keep the LAN controller in reset state
 	 * for a while. (200 usec)
-	 * Fortunatelly, enough wait time is already inserted in pll_init()
+	 * Fortunately, enough wait time is already inserted in pll_init()
 	 * function. So we do not have to wait here.
 	 */
 	support_card_reset_deassert();
@@ -213,11 +214,11 @@ static void detect_num_flash_banks(void)
 
 	debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
 }
-#else /* ONFIG_SYS_NO_FLASH */
+#else /* CONFIG_SYS_NO_FLASH */
 void detect_num_flash_banks(void)
 {
 };
-#endif /* ONFIG_SYS_NO_FLASH */
+#endif /* CONFIG_SYS_NO_FLASH */
 
 void support_card_late_init(void)
 {