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authorYe Li <ye.li@nxp.com>2016-05-16 14:04:53 +0800
committerYe Li <ye.li@nxp.com>2017-04-05 14:04:43 +0800
commit4976f8f1adc5518135f663ef33991151be9d5067 (patch)
treef20c98e7e39f0e2481d3afab50826c3e17e1eea8
parent2906317e68d2f5a9ff75b43c1b54c768098fa7f2 (diff)
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MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLL
In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7f00c72e17e4e440df62aa4945a619fdbc9cfd8f)
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 7c9258b..ee796bc 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -802,6 +802,16 @@ int overwrite_console(void)
int board_eth_init(bd_t *bis)
{
+ if (is_mx6dqp()) {
+ int ret;
+
+ /* select ENET MAC0 TX clock from PLL */
+ imx_iomux_set_gpr_register(5, 9, 1, 1);
+ ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+ if (ret)
+ printf("Error fec anatop clock settings!\n");
+ }
+
setup_iomux_enet();
return cpu_eth_init(bis);