summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorYork Sun <yorksun@freescale.com>2011-01-10 12:02:57 +0000
committerKumar Gala <galak@kernel.crashing.org>2011-01-19 22:58:23 -0600
commit47df8f03f4cae5cec1f42856916a3dd0d0460dc1 (patch)
tree5c46a33980469680eeba453a2f18652495633b13
parentdd12768974358e9f03147c3bffc54b619308f318 (diff)
downloadu-boot-imx-47df8f03f4cae5cec1f42856916a3dd0d0460dc1.zip
u-boot-imx-47df8f03f4cae5cec1f42856916a3dd0d0460dc1.tar.gz
u-boot-imx-47df8f03f4cae5cec1f42856916a3dd0d0460dc1.tar.bz2
mpc8xxx: Enable ECC on/off control in hwconfig
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/options.c9
-rw-r--r--doc/README.fsl-ddr7
2 files changed, 13 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 0e7097b..55dff43 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -98,10 +98,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Operational Mode Paramters */
/* Pick ECC modes */
-#ifdef CONFIG_DDR_ECC
- popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */
-#else
popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
+#ifdef CONFIG_DDR_ECC
+ if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
+ if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
+ popts->ECC_mode = 1;
+ } else
+ popts->ECC_mode = 1;
#endif
popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 1657ef6..9e3c539 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -78,6 +78,13 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig.
Syntax is:
hwconfig=fsl_ddr:addr_hash=true
+Memory controller ECC on/off
+============================
+If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
+ECC can be turned on/off by hwconfig.
+
+Syntax is
+hwconfig=fsl_ddr:ecc=off
Memory testing options for mpc85xx
==================================