diff options
author | Alessandro Rubini <rubini@unipv.it> | 2009-12-05 13:39:31 +0100 |
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committer | Anatolij Gustschin <agust@denx.de> | 2010-01-27 21:23:14 +0100 |
commit | 3e446cbdf30221b9ca3a89b0f5abbfc691ce7755 (patch) | |
tree | 7bce6b7c5cdc945580827b0ea51b6a5654761236 | |
parent | 9b208ece0a4e040774e24990b7cb6f0ad0ca4cc7 (diff) | |
download | u-boot-imx-3e446cbdf30221b9ca3a89b0f5abbfc691ce7755.zip u-boot-imx-3e446cbdf30221b9ca3a89b0f5abbfc691ce7755.tar.gz u-boot-imx-3e446cbdf30221b9ca3a89b0f5abbfc691ce7755.tar.bz2 |
video: add amba-clcd prime-cell
This adds support for the CLCD logic cell. It accepts precompiled
register values for specific configuration through a board-supplied
data structure. It is used by the Nomadik nhk8815, added by a later
patch in this series.
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
-rw-r--r-- | drivers/video/Makefile | 1 | ||||
-rw-r--r-- | drivers/video/amba.c | 79 | ||||
-rw-r--r-- | include/amba_clcd.h | 77 |
3 files changed, 157 insertions, 0 deletions
diff --git a/drivers/video/Makefile b/drivers/video/Makefile index bb6b5a0..a5e339a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o +COBJS-$(CONFIG_VIDEO_AMBA) += amba.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o diff --git a/drivers/video/amba.c b/drivers/video/amba.c new file mode 100644 index 0000000..ffa1c39 --- /dev/null +++ b/drivers/video/amba.c @@ -0,0 +1,79 @@ +/* + * Driver for AMBA PrimeCell CLCD + * + * Copyright (C) 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <lcd.h> +#include <amba_clcd.h> + +/* These variables are required by lcd.c -- although it sets them by itself */ +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; +void *lcd_base; +void *lcd_console_address; +short console_col; +short console_row; + +/* + * To use this driver you need to provide the following in board files: + * a panel_info definition + * an lcd_enable function (can't define a weak default with current code) + */ + +/* There is nothing to do with color registers, we use true color */ +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ + return; +} + +/* Low level initialization of the logic cell: depends on panel_info */ +void lcd_ctrl_init(void *lcdbase) +{ + struct clcd_config *config; + struct clcd_registers *regs; + u32 cntl; + + config = panel_info.priv; + regs = config->address; + cntl = config->cntl & ~CNTL_LCDEN; + + /* Lazily, just copy the registers over: first control with disable */ + writel(cntl, ®s->cntl); + + writel(config->tim0, ®s->tim0); + writel(config->tim1, ®s->tim1); + writel(config->tim2, ®s->tim2); + writel(config->tim3, ®s->tim3); + writel((u32)lcdbase, ®s->ubas); + /* finally, enable */ + writel(cntl | CNTL_LCDEN, ®s->cntl); +} + +/* This is trivial, and copied from atmel_lcdfb.c */ +ulong calc_fbsize(void) +{ + return ((panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; +} diff --git a/include/amba_clcd.h b/include/amba_clcd.h new file mode 100644 index 0000000..db80517 --- /dev/null +++ b/include/amba_clcd.h @@ -0,0 +1,77 @@ +/* + * Register definitions for the AMBA CLCD logic cell. + * + * derived from David A Rusling, although rearranged as a C structure + * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel. + * + * Copyright (C) 2001 ARM Limited + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * CLCD Controller Internal Register addresses + */ +struct clcd_registers { + u32 tim0; /* 0x00 */ + u32 tim1; + u32 tim2; + u32 tim3; + u32 ubas; /* 0x10 */ + u32 lbas; +#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW) + u32 ienb; + u32 cntl; +#else /* Someone rearranged these two registers on the Versatile */ + u32 cntl; + u32 ienb; +#endif + u32 stat; /* 0x20 */ + u32 intr; + u32 ucur; + u32 lcur; + u32 unused[0x74]; /* 0x030..0x1ff */ + u32 palette[0x80]; /* 0x200..0x3ff */ +}; + +/* Bit definition for TIM2 */ +#define TIM2_CLKSEL (1 << 5) +#define TIM2_IVS (1 << 11) +#define TIM2_IHS (1 << 12) +#define TIM2_IPC (1 << 13) +#define TIM2_IOE (1 << 14) +#define TIM2_BCD (1 << 26) + +/* Bit definitions for control register */ +#define CNTL_LCDEN (1 << 0) +#define CNTL_LCDBPP1 (0 << 1) +#define CNTL_LCDBPP2 (1 << 1) +#define CNTL_LCDBPP4 (2 << 1) +#define CNTL_LCDBPP8 (3 << 1) +#define CNTL_LCDBPP16 (4 << 1) +#define CNTL_LCDBPP16_565 (6 << 1) +#define CNTL_LCDBPP24 (5 << 1) +#define CNTL_LCDBW (1 << 4) +#define CNTL_LCDTFT (1 << 5) +#define CNTL_LCDMONO8 (1 << 6) +#define CNTL_LCDDUAL (1 << 7) +#define CNTL_BGR (1 << 8) +#define CNTL_BEBO (1 << 9) +#define CNTL_BEPO (1 << 10) +#define CNTL_LCDPWR (1 << 11) +#define CNTL_LCDVCOMP(x) ((x) << 12) +#define CNTL_LDMAFIFOTIME (1 << 15) +#define CNTL_WATERMARK (1 << 16) + +/* u-boot specific: information passed by the board file */ +struct clcd_config { + struct clcd_registers *address; + u32 tim0; + u32 tim1; + u32 tim2; + u32 tim3; + u32 cntl; + unsigned long pixclock; +}; |