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| author | Simon Glass <sjg@chromium.org> | 2015-01-27 22:13:33 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-02-05 22:16:43 -0700 |
| commit | 2d934e5703b712686c3ec67f6d5eeb137c68805d (patch) | |
| tree | 31052345a6556760420f3c5435eae749d359e255 | |
| parent | eea0f11278d9104960dfb1fbfcddfb796a3e0bb5 (diff) | |
| download | u-boot-imx-2d934e5703b712686c3ec67f6d5eeb137c68805d.zip u-boot-imx-2d934e5703b712686c3ec67f6d5eeb137c68805d.tar.gz u-boot-imx-2d934e5703b712686c3ec67f6d5eeb137c68805d.tar.bz2 | |
x86: Rename MMCONF_BASE_ADDRESS and make it common across x86
This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/x86/Kconfig | 14 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/sdram.c | 2 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 | ||||
| -rw-r--r-- | board/google/chromebook_link/Kconfig | 3 |
4 files changed, 17 insertions, 4 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 90e828a..928fc60 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -356,4 +356,18 @@ source "board/google/chromebook_link/Kconfig" source "board/intel/crownbay/Kconfig" +config PCIE_ECAM_BASE + hex + default 0xe0000000 + help + This is the memory-mapped address of PCI configuration space, which + is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. It can be set up almost + anywhere. Before it is set up, it is possible to access PCI + configuration space through I/O access, but memory access is more + convenient. Using this, PCI can be scanned and configured. This + should be set to a region that does not conflict with memory + assigned to PCI devices - i.e. the memory and prefetch regions, as + passed to pci_set_region(). + endmenu diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 4963448..766b385 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -757,7 +757,7 @@ int dram_init(void) .mchbar = DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_PCIE_ECAM_BASE, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index cf7457f..c960525 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -43,7 +43,7 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 /* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS +#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define EPBAR 0x40 diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 33a31f3..ea45472 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,8 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192 -config MMCONF_BASE_ADDRESS - hex +config PCIE_ECAM_BASE default 0xf0000000 config EARLY_POST_CROS_EC |