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authorShengzhou Liu <Shengzhou.Liu@freescale.com>2014-10-27 10:08:16 +0800
committerYork Sun <yorksun@freescale.com>2014-12-05 08:06:07 -0800
commit2519cb344ee7911ab2f6643449f5dcc32cec9653 (patch)
treed7b1629ce50e25283c726bb042f3cea32e8580e4
parentbcb60cb9c42eaef9292c02c60742654a3151883e (diff)
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powerpc/t2080: add serdes2 protocol 0x2e
Add serdes2 protocol 0x2e. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r--arch/powerpc/cpu/mpc85xx/t2080_serdes.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index 7138bb4..c65f41d 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -169,6 +169,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
{0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },