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authorChunhe Lan <Chunhe.Lan@freescale.com>2014-10-20 16:03:15 +0800
committerYork Sun <yorksun@freescale.com>2014-11-19 10:28:30 -0800
commit1b5c2b51337bb360555f2fb2f6e671fd8662a8d2 (patch)
tree544dfd243b93fb8dd412c677b29659acdef73a82
parente9caf760326efb7db9bb4d06d2e76e842741225a (diff)
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powerpc/t4rdb: Fix CPLD timing
This fixes CPLD timing from previous commit ab06b236f76cfa42f264ee161be190b3e479298f. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: This is the difference between v2 and v1 patch] Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r--include/configs/T4240RDB.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index e639e1d..48b8dc7 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -533,7 +533,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0