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| author | Richard Zhu <r65037@freescale.com> | 2013-04-16 09:43:06 +0800 |
|---|---|---|
| committer | Richard Zhu <r65037@freescale.com> | 2013-04-16 13:49:36 +0800 |
| commit | 18fdfe698447a9a38ce1503380c50c2073321672 (patch) | |
| tree | 20f3b9ce9fc722be81fa8cf8c57c88a5e3b06f47 | |
| parent | 75a15f1dc81d03aa90d38edf4b775b8d57166f3f (diff) | |
| download | u-boot-imx-18fdfe698447a9a38ce1503380c50c2073321672.zip u-boot-imx-18fdfe698447a9a38ce1503380c50c2073321672.tar.gz u-boot-imx-18fdfe698447a9a38ce1503380c50c2073321672.tar.bz2 | |
ENGR00254470-4 mx6q-hdmidongle:sata device can't work properly on most boards
Revert "ENGR00241595-4 mx6q-hdmidongle:Enable SATA PHY PDDQ default"
This reverts commit d33eefe083563a082840a46ec9cac21f98fad550.
Reasons:
* according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is
powered down automatically according to SATA controller
power mode SATA port support Disable/Slumber/Partial/Enabled(OOB)
The SATA PHY PDDQ mode is one-shot and recommeded to be used for test,
SATA would not work properly if the PHY PDDQ mode is enabled in U-boot.
Signed-off-by: Richard Zhu <r65037@freescale.com>
| -rw-r--r-- | board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c b/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c index 198ccc4..6677ad4 100644 --- a/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c +++ b/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c @@ -219,8 +219,6 @@ void board_mmu_init(void) #define ANATOP_PLL_PWDN_MASK 0x00001000 #define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800 #define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000 -#define PORT_PHY_CTL 0x178 -#define PORT_PHY_CTL_PDDQ_LOC 0x100000 /* Note: udelay() is not accurate for i2c timing */ static void __udelay(int time) @@ -278,16 +276,6 @@ static int setup_sata(void) * */ reg |= 0x59124c6; writel(reg, IOMUXC_BASE_ADDR + 0x34); - /* FIXME */ - /* - * It needs to wait SATA PHY initialize completed, otherwise write the - * PORT_PHY_CTL will fail, then can't enable PDDQ which let PHY entry LPM - * Currently set it as 1ms. - */ - __udelay(1000); - /* Enable PDDQ mode in default */ - writel(readl(SATA_ARB_BASE_ADDR + PORT_PHY_CTL) | PORT_PHY_CTL_PDDQ_LOC, - SATA_ARB_BASE_ADDR + PORT_PHY_CTL); return 0; } @@ -1421,10 +1409,6 @@ int checkboard(void) printf("UNKNOWN\n"); break; } - if (cpu_is_mx6q()) - printf("SATA PDDQ: %s\n", ((readl(SATA_ARB_BASE_ADDR - + PORT_PHY_CTL) - & PORT_PHY_CTL_PDDQ_LOC)>>20) ? "enabled" : "disabled"); return 0; } |