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authorStefan Bigler <stefan.bigler@keymile.com>2011-07-18 15:25:11 +0200
committerScott Wood <scottwood@freescale.com>2011-10-03 18:35:11 -0500
commit156800905a17f3ce1638f89fb0f7b4bf55a1fa02 (patch)
tree835007eaf4dabbe6dab047a6dc9a3b5a72621479
parent7b8ffea2ac44097ed1c99ba70b8c6a4cf12ba0b4 (diff)
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nand: increase chip_delay in mv kirkwood nand driver
The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay. The Data Transfer from Cell to Register is >= 35us. Other Vendors and older chips normally use >= 25us. To have enough margin 40us is selected. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
-rw-r--r--drivers/mtd/nand/kirkwood_nand.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index 376378e..bdab5aa 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -76,7 +76,7 @@ int board_nand_init(struct nand_chip *nand)
nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = kw_nand_hwcontrol;
- nand->chip_delay = 30;
+ nand->chip_delay = 40;
nand->select_chip = kw_nand_select_chip;
return 0;
}