ENGR00236472 Update DDR script of ARD solo emulation

Update DDR script of ARD solo emulation, the ddr script
based on the following commit from ddr-scripts-rel git:
dfde48e Added MX6Solo ARD DDR3 init.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>

1 files changed, 56 insertions, 77 deletions

diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S
index 24cb155..a7538e6 100644
--- a/board/freescale/mx6q_sabreauto/flash_header.S
+++ b/board/freescale/mx6q_sabreauto/flash_header.S
@@ -54,8 +54,8 @@ image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
 plugin:           .word 0x0
 
 #if defined CONFIG_MX6SOLO_DDR3
-dcd_hdr:          .word 0x408802D2 /* Tag=0xD2, Len=80*8 + 4 + 4, Ver=0x40 */
-write_dcd_cmd:    .word 0x048402CC /* Tag=0xCC, Len=80*8 + 4, Param=0x04 */
+dcd_hdr:          .word 0x40E001D2 /* Tag=0xD2, Len=59*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04DC01CC /* Tag=0xCC, Len=80*8 + 4, Param=0x04 */
 
 /* DCD */
 /* DDR3 initialization based on the MX6Solo Auto Reference Design (ARD) */
@@ -70,89 +70,68 @@ MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
 MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
 MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
 /* CONTROLE */
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x000c0030)
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
 /* DATA STROBE */
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000038)
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000038)
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000038)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000038)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000038)
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000038)
-MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000038)
-MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000038)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000028)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000028)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000028)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000028)
 /* DATA */
-MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
-MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
-MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
-MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
-MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
-MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
-MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
-MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
-MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
-
-MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
-MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
-MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
-MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
-MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
-MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
-MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
-MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x000C0030)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x764, 0x00000028)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x770, 0x00000028)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x778, 0x00000028)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x77c, 0x00000028)
+
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x470, 0x00000028)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x474, 0x00000028)
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x478, 0x00000028)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x47c, 0x00000028)
 /* ZQ */
-MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
-MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(27, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
 /* Write leveling */
-MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x0040003c)
-MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0032003e)
+MXC_DCD_ITEM(28, MMDC_P0_BASE_ADDR + 0x80c, 0x001f001f)
+MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x810, 0x001f001f)
 
-MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x83c, 0x42350231)
-MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x840, 0x021a0218)
-MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x848, 0x4b4b4e49)
-MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x850, 0x3f3f3035)
+MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x83c, 0x421c0216)
+MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x840, 0x017b017a)
+MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x848, 0x4b4a4e4c)
+MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x850, 0x3f3f3334)
 /* Read data bit delay */
-MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
-MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
-MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
-MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(53, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
-MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
-MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
-MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
 
 /* Complete calibration by forced measurement */
-MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
-MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
-
-MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
-MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
-MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x00c, 0x696d5323)
-MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
-MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
-MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
-MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
-MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x030, 0x006d0e21)
-MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
-MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x000, 0x84190000)
-MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
-MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
-MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
-MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
-MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
-MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
-MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
-MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
-MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
-MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x004, 0x00011006)
-MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x004, 0x00020025)
+MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x00c, 0x676b5313)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8b63)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
+MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x030, 0x006b1023)
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x000, 0x84190000)
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00025565)
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
 
 #elif defined CONFIG_LPDDR2
 dcd_hdr:          .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4, Ver=0x40 */